Unimportance of geometric nonlinearity in analysis of flanged joints with metal-to-metal contact

Gasketless flanged joints with metal to metal contact offer some advantages over gasketed joints such as lower weight and better fatigue life. Design of such joints is often based on finite element analyses, and complicated by the fact that the area of contact between the flanges changes upon application of loads. Such analyses can be done using commercial software, which can incorporate geometrical nonlinearities as well as contact nonlinearities. Engineering intuition suggests that the role of geometrical nonlinearities might be small for such problems. However, many engineers continue to use the fully nonlinear analyses. Our aim in this paper is simply to put on record that significant savings in time can be obtained by “turning off” geometric nonlinearities in such analyses, with negligible loss of accuracy. To this end, a nonautomated implementation of the basic ideas is first demonstrated for a simple geometry; more automated analyses for a more general geometry follow.     

Electrical properties of Ta/sub 2/O/sub 5/ gate dielectric on strained-Si

High dielectric constant (high-k) thin Ta/sub 2/O/sub 5/ films have been deposited on tensilely strained silicon (strained-Si) layers using a microwave plasma enhanced chemical vapour deposition technique at a low temperature. The deposited Ta/sub 2/O/sub 5/ films show good electrical properties as gate dielectrics and are suitable for microelectronic applications. The feasibility of integration of strained-Si and high-k dielectrics has been demonstrated.     

The impact of trench isolation on latch-up immunity in bulknonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates     

Analysis of surface preparation treatments for coating tungsten carbide substrates with diamond thin films

The effect of various substrate surface treatments on (i) the pre-growth topography and composition of the treated substrate, and (ii) the quality of diamond thin films produced by hot-filament chemical vapour deposition on tungsten carbide substrates, is reported. Two different substrate grain sizes were subjected to various surface treatments. They were then examined for surface material composition and topography using scanning electron microscopy and X-ray diffraction (XRD). Subsequently, diamond films were deposited on the samples and their quality analysed by Raman spectroscopy and XRD techniques. These analyses do not indicate a strong dependence between the substrate grain size and film quality. However, the surface-treatment method affects the resulting substrate surface topography and film quality. This revised version was published online in November 2006 with corrections to the Cover Date.     

A low-voltage triggering SCR for on-chip ESD protection at outputand input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V     

Modified technique of using conventional slider boat for liquid phase epitaxy of silicon for solar cell application

Epitaxial layers of silicon are grown on single crystal Si- substrate from a solution of silicon in indium using conventional graphite slider boat technique. The important problems of natural convection due to lower density of silicon compared to indium,poor wetting of substrate due to high angle of contact of indium solution on silicon substrate resulting in poor nucleation, melt removal from the growth substrate and saturation wafer associated with LPE in this technique are practically eliminated using sandwich method with simple modifications of the boat and the method of growth. Some experimental studies on the effect of different surface preparations of growth substrate are also reported. Growth results are shown and discussed. Further, improvization of slider boat to facilitate better study of growth parameters is suggested in the line of modification already carried out.     

Tribological behavior of hafnium diboride thin films

Transition metal diborides and their coatings offer an excellent combination of high hardness, high chemical stability and high thermal conductivity, thus they are excellent candidates for a wide range of tribological applications. In this work, stoichiometric hafnium diboride films were grown by chemical vapor deposition from a single-source, heteroatom-free precursor Hf(BH₄)₄ under conditions that afford highly conformal and smooth films. HfB₂ films of thickness ∼ 0.6 μm deposited on steel substrates were subjected to pin-on-disk wear testing against a counter face disc of AISI 440C martensitic stainless steel. Based on wear measurements, both as-deposited (X-ray amorphous) and annealed (nanocrystalline) samples showed very high wear resistance compared to uncoated samples. For the annealed samples, SEM analysis indicated the formation of a wear resistant composite body in the wear scar, even at depths far exceeding the film thickness, which appears to dramatically improve wear resistance. No mild-to-severe wear transition was observed which indicates that mild wear occurred throughout the wear test. This ensemble of results, when considered in the light of high contact pressures (∼ 700 MPa) used in the study, makes the HfB₂ material potentially attractive for wear-resistant applications.     

A Branching Time Temporal Framework for Quantitative Reasoning

Temporal logics such as Computation Tree Logic (CTL) and Linear Temporal Logic (LTL) have become popular for specifying temporal properties over a wide variety of planning and verification problems. In this paper we work towards building a generalized framework for automated reasoning based on temporal logics. We present a powerful extension of CTL with first-order quantification over the set of reachable states for reasoning about extremal properties of weighted labeled transition systems in general. The proposed logic, which we call Weighted Quantified Computation Tree Logic (WQCTL), captures the essential elements common to the domain of planning and verification problems and can thereby be used as an effective specification language in both domains. We show that in spite of the rich, expressive power of the logic, we are able to evaluate WQCTL formulas in time polynomial in the size of the state space times the length of the formula. Wepresent experimental results on the WQCTL verifier.