Impact of Tellurium Precipitates in CdZnTe Substrates on MBE HgCdTe Deposition

State-of-the-art (112)B CdZnTe substrates were examined for near-surface tellurium precipitate-related defects. The Te precipitate density was observed to be fairly uniform throughout the bulk of the wafer, including the near-surface region. After a molecular beam epitaxy (MBE) preparation etch, exposed Te precipitates, small pits, and bumps on the (112)B surface of the CdZnTe wafer were observed. From near-infrared and dark field microscopy, the bumps and small pits on the CdZnTe surface are associated with strings of Te precipitates. Raised bumps are Te precipitates near the surface of the (112)B CdZnTe where the MBE preparation etch has not yet exposed the Te precipitate(s). An exposed Te precipitate sticking above the etched CdZnTe surface plane occurs when the MBE preparation etch rapidly undercuts a Te precipitate. Shallow surface pits are formed when the Te precipitate is completely undercut from the surrounding (112)B surface plane. The Te precipitate that was previously located at the center of the pit is liberated by the MBE preparation etch process.     

Processing and characterization of a-Si:H photoresists for a vacuum-compatible photolithography process

The vision of achieving a completely in-vacuum process for fabricating HgCdTe detector arrays is contingent on the availability of a vacuumcompatible photolithography technology. One such technology for vacuum photolithography involves the use of amorphous-hydrogenated Si (a-Si:H) as a photoresist. In this work, we deposit a-Si:H resists via plasma-enhanced chemical-vapor deposition (PECVD) using an Ar-diluted silane precursor. The resists are then patterned via excimer laser exposure and development etched in a hydrogen plasma where etch selectivities between unexposed and exposed regions exceed 600:1. To determine the best conditions for the technique, we investigate the effects of different exposure environments and carry out an analysis of the a-Si:H surfaces before and after development etching. Analysis via transmission electron microscopy (TEM) reveals that the excimer-exposed surfaces are polycrystalline in nature, indicating that the mechanism for pattern generation in this study is based on melting and crystallization. To demonstrate pattern transfer, underlying CdTe films were etched (after development of the resist) in an electron cyclotron resonance (ECR) plasma, where etch selectivities of approximately 8:1 have been achieved. The significance of this work is the demonstration of laser-induced poly-Si as an etching mask for vacuum-compatible photolithography.     

Managing computer networks using peer-to-peer technologies

Peer-to-peer systems and network management are usually related to each other because the traffic loads of P2P systems have to be controlled to avoid regular network services becoming unavailable due to network congestion. In this context, from a network operation point of view, P2P systems often mean problems. In this article we take a different perspective and look at P2P technologies as an alternative to improve current network management solutions. We introduce an approach where P2P networks are used as flexible interdomain distributed management systems able to provide facilities often absent in traditional management systems. We present three examples of P2P-based network management: how managed network views can be shared in a P2P network, how P2P-based application layer routing can improve connectivity between management entities, and how groups of peers can be used to process management tasks in a balanced way. Our main goal is to show that P2P technologies are a feasible tool for network management, and thus motivate further investigations on the subject.     

MESFET DC model parameter extraction using Quantum Particle Swarm Optimization

This paper presents two techniques for DC model parameter extraction for a Gallium Arsenide (GaAs) based MEtal Semiconductor Field Effect Transistor (MESFET) device. The proposed methods uses Particle Swarm Optimization (PSO) and Quantum Particle Swarm Optimization (QPSO) methods for optimizing the difference between measured data and simulated data. Simulated data are obtained by using four different popular DC models. These techniques avoid complex computational steps involved in traditional parameter extraction techniques. The performance comparison in terms of quality of solution and execution time of classical PSO and QPSO to extract the model parameters are presented. The validity of this approach is verified by comparing the simulated and measured results of a fabricated GaAs MESFET device with gate length of 0.7 μm and gate width of 600 μm (4 × 150). Simulation results indicate that both the technique based on PSO and QPSO accurately extracts the model parameters of MESFET.     

Improved Message Forwarding for Multi-Hop HaRTES Real-Time Ethernet Networks

Nowadays, switched Ethernet networks are used in complex systems that encompass tens to hundreds of nodes and thousands of signals. Such scenarios require multi-switch architectures where communications frequently occur in multiple hops. In this paper we investigate techniques to allow efficient multi-hop communication using HaRTES switches. These are modified Ethernet switches that provide real-time traffic scheduling, dynamic bandwidth management and temporal isolation between real-time and non-real-time traffic. This paper addresses the problem of forwarding traffic in HaRTES networks. Two methods have been recently proposed, namely Distributed Global Scheduling (DGS) that buffers traffic between switches, and Reduced Buffering Scheme (RBS), that uses immediate forwarding. In this paper, we discuss the design and implementation of RBS within HaRTES and we carry out an experimental validation with a prototype implementation. Then, we carry out a comparison between RBS and DGS using worst-case response time analysis and simulation. The comparison clearly establishes the superiority of RBS concerning end-to-end response times. In fact, with sample message sets, we achieved reductions in end-to-end delay that were as high as 80 %.     

Effects of Phonon Confinement on Anomalous Thermalization,Energy Transfer,and Upconversion in Ln3+‐Doped Gd2O3 Nanotubes

There is a growing interest in understanding how size‐dependent quantum confinement affects the photoluminescence efficiency, excited‐state dynamics, energy‐transfer and thermalization phenomena in nanophosphors. For lanthanide (Ln³⁺)‐doped nanocrystals, despite the localized 4f states, confinement effects are induced mostly via electron–phonon interactions. In particular, the anomalous thermalization reported so far for a handful of Ln³⁺‐doped nanocrystals has been rationalized by the absence of low‐frequency phonon modes. This nanoconfinement may further impact on the Ln³⁺ luminescence dynamics, such as phonon‐assisted energy transfer or upconversion processes. Here, intriguing and unprecedented anomalous thermalization in Gd₂O₃:Eu³⁺ and Gd₂O₃:Yb³⁺,Er³⁺ nanotubes, exhibiting up to one order of magnitude larger than previously reported for similar materials, is reported. This anomalous thermalization induces unexpected energy transfer from Eu³⁺ C₂ to S₆ crystallographic sites, at 11 K, and ²H_11/2 → ⁴I_15/2 Er³⁺ upconversion emission; it is interpreted on the basis of the discretization of the phonon density of states, easily tuned by varying the annealing temperature (923–1123 K) in the synthesis procedure, and/or the Ln³⁺ concentration (0.16–6.60%).     

Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology

In digital CMOS circuits, parametric yield improvement may be achieved by reducing the variability of performance and power consumption of individual cell instances. Such improvement of variation robustness can be attained by evaluating parameter variation impact at gate level. Statistical characterization of logic gates are usually obtained by computationally expensive electrical simulations. An efficient gate delay variability estimation method is proposed for variability-aware design. The proposed method has been applied to different topologies (transistor network arrangements) and CMOS gates, and it has been compared to Monte Carlo simulations for data validation, resulting in computation time savings.     

Identity-based key management in mobile ad hoc networks: techniques and applications [dependability in the ubiquitous wireless access]

Security is one of the major issues in MANETs. Their natural characteristics make them vulnerable to numerous severe attacks. It is widely acknowledged that cryptography provides a set of strong techniques against most vulnerabilities. Several cryptographic mechanisms for MANETs can be found in the literature. Among them, identity-based cryptographic mechanisms and key management schemes are proposed to simplify key management and to reduce the memory storage cost. This article presents the most important ID-based key management schemes, discussing their approaches, strengths, and weaknesses, and comparing their main features. It also presents the main IDbased key management application fields on MANETs. In this way it can be useful for users and researchers as a starting point on ID-based key management and its possible uses in MANETs.     

Fully digital BPSK demodulator for satellite supressed carrier telecommand system

In this paper, we present the design of a fully digital binary phase shift keying demodulator for application in satellite high‐rate suppressed carrier telecommand system. The proposed system digitalizes the received signal in the intermediate frequency stage using bandpass sampling technique, and the resulting baseband signal is used to synchronization of symbol and phase and to bit detection. The design of all functional modules is presented in details. Another innovation presented in this work is the inclusion of a non‐linearity in the phase synchronizer module to permit its operation independent from the signal amplitude. Moreover, aiming the characterization and performance evaluation of the system, we do some original mathematical analyses. Finally, test results show that the demodulator complies all the project requirements, and the prototype implementation loss, in terms of bit energy to noise power density ratio, is less than 0.3 dB. Copyright © 2016 John Wiley & Sons, Ltd.