Interfacial reactions in the Sn-(Ag)/(Ni,V) couples and phase equilibria of the Sn-Ni-V system at the Sn-Rich corner

Ni-7wt.%V is commonly used as the barrier layer material in the under-bump metallurgy in the microelectronic industry. Although interfacial reactions between various solders with the nickel substrate have been investigated intensively, the effects of vanadium addition upon the solder/(Ni,V) interfacial reactions have not been studied. Sn/(Ni,V) and Sn-Ag/(Ni,V) interfacial reactions at 250°C were investigated in this study using the reaction couple technique. The vanadium contents of the (Ni,V) substrates examined in this study are 3 wt.%, 5 wt.%, 7 wt.%, and 12 wt.% and the reaction time is 12 h. The results indicate that when the vanadium contents in the (Ni,V) substrate are 5 wt.% and higher, the Sn/(Ni,V) and Sn-Ag/(Ni,V) interfacial reactions are different from those in the solder/Ni couples. Besides the Ni₃Sn₄ phase as commonly formed in the reaction with Ni substrate, a new ternary T phase has been found, and the reaction path is L/Ni₃Sn₄/T/(Ni,V). A 250°C Sn-Ni-V isothermal section is proposed based on the three constituent binary systems and limited experimental results obtained in this study. The reaction path is illustrated with the proposed Sn-Ni-V isothermal section. No stable ternary Sn-Ni-V phase is found from the phase equilibria study, and the new T phase is likely a metastable phase.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

A better channel coding for a Link‐16 waveform in pulsed‐noise interference

Link‐16 is a tactical data link currently used by North Atlantic Treaty Organization (NATO) countries, the United States and its allies. The Link‐16 waveform features Reed–Solomon codes for channel coding, cyclic code‐shift keying for 32‐ary baseband symbol modulation, minimum‐shift keying for waveform modulation, and frequency hopping for transmission security. In addition to the original errors‐only decoding of Reed–Solomon codes, both an errors‐and‐erasures decoding (EED) and a special concatenated coding are proposed in this paper to determine a better channel coding scheme for a Link‐16 waveform with noncoherent detection in the presence of pulsed‐noise interference (PNI). The investigation is first carried out both analytically and by simulation for the original Link‐16 waveform transmitted over AWGN. It is then accomplished analytically for the proposed waveforms in both AWGN and PNI. The results show that EED achieves the best error rate performance for a Link‐16 waveform in both AWGN and PNI when the signal‐to‐noise ratio is relatively small. When both the signal‐to‐noise ratio is sufficiently large and the fraction active time of PNI is small, the proposed concatenated coding outperforms both EED and errors‐only decoding. Copyright © 2012 John Wiley & Sons, Ltd.     

GaAsSb/InAlAs PA DHBTs Grown by Production MBE

The epi material growth of GaAsSb based DHBTs with InAlAs emitters are investigated using a 4 × 100mm multi-wafer production Riber 49 MBE reactor fully equipped with real-time in-situ sensors including an absorption band edge spectroscope and an optical-based flux monitor. The state-of-the-art hole mobilities are obtained from 100nm thick carbon-doped GaAsSb. A Sb composition variation of less than ± 0.1 atomic percent across a 4 × 100mm platen configuration has been achieved. The large area InAlAs/GaAsSb/InP DHBT device demonstrates excellent DC characteristics,such as BVCEO＞6V and a DC current gain of 45 at 1kA/cm2 for an emitter size of 50μm × 50μm. The devices have a 40nm thick GaAsSb base with p-doping of 4. 5 × 1019cm-3 . Devices with an emitter size of 4μm × 30μm have a current gain variation less than 2% across the fully processed 100mm wafer. ft and fmax are over 50GHz,with a power efficiency of 50% ,which are comparable to standard power GaAs HBT results. These results demonstrate the potential application of GaAsSb/InP DHBT for power amplifiers and the feasibility of multi-wafer MBE for mass production of GaAsSb-based HBTs.     

Micro FET pressure sensor manufactured using CMOS-MEMS technique

The fabrication of a micro field effect transistor (FET) pressure sensor using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process has been investigated. The pressure sensor is composed of 16 sensing cells in parallel, and each sensing cell includes a suspended membrane and an NMOS. The suspended membrane is the movable gate of the NMOS. The pressure sensor needs a post-process to obtain the suspended membrane after the CMOS process. The post-process employs etchants to etch the sacrificial layers to release the suspended membrane, and then a low-pressure chemical vapor deposition (LPCVD) parylene is used to seal the etching holes in the pressure sensor. The pressure sensor produces a change in current when applying a pressure to the sensing cells. Experimental results show that the pressure sensor has a sensitivity of 0.022 μA/kPa in the pressure range of 0–500 kPa.     

Augmented Cell Performance of NO-Based Storage Dielectric by N$_2$ O-Treated Nitride Film for Trench DRAM

Owing to the delayed introduction of high-kappa storage dielectric for trench DRAM, a new technology to extend the existing NO storage dielectric becomes a prerequisite. For trench DRAM, the nitride film of NO-based storage dielectric has been proved to possess higher quality by proper treatment, which enables further reduction in nitride thickness and extension of scaling limit for the existing storage dielectric. A 164% leakage current improvement without sacrificing the cell capacitance can be achieved through this process, while keeping the outstanding reliability performance of less than 438 ppm failure rate after a ten-year operation. Most importantly, this new process can be fully integrated into incumbent furnace process, which means that no additional tool investment is required, and it is crucial for trench DRAM manufacturers to maintain their competitive advantage before the high-k material prevails at 65 nm technology node.     

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.     

Experimental Evidence for Formation of Ni-Al Compound in Flip-Chip Joints Under Current Stressing

The materials interactions on the under bump metallization (UBM) side of flip-chip solder joints during current stressing were studied by using high-resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM). Flip-chip solder joints with sputtered Al/Ni(V)/Cu UBM were subjected to current stressing at an ambient temperature of 150°C. It was found that a layer of Ni-Al phase, presumably NiAl₃ according to energy-dispersive x-ray spectroscopy (EDX) measurements, was observed at the Al/Ni(V) interface. In addition, evidence for the formation of a nonconductive oxide layer at the NiAl₃/Ni(V) interface was observed. This nonconductive oxide layer was responsible for diverting electron current away from the porous region.     

A PARALLEL COUPLED-LINE FILTER USING VLSI BACKEND INTERCONNECT WITH HIGH RESISTIVITY SUBSTRATE

This paper reports our progress in developing parallel coupled-line filters based on Si-based VLSI backend interconnects for millimeter-wave applications. The resonant frequency of this coupled-line filter increases with increasing spacing-gap and with increasing IDM thickness. By using high resistivity substrate, the parallel coupled-line band-pass filter is extremely effective in reducing substrate loss, and also provides very low insertion loss, even at the millimeter-wave regime. In addition, the parallel coupled-line filter suitable for advanced system-on-a-chips at the millimeter wave application achieves high performance characteristics, which show low insertion loss, wide band, and compatibility with standard VLSI process.     

A better technique using multisegment modeling and analysis of high-density and high-speed connectors

A useful and rather new simulation technique for connectors up to 6.25 GHz is presented and discussed in this paper. The proposed model extracts electrical parameters of a connector using time-domain reflectometry (TDR) measurements. A new technique was developed to obtain accurate impedance profiles using TDR and a multisegment approach that is effectively a distributed coupled model. The parameter extraction and characterization of connectors are discussed. The performance of the proposed segmented transmission line model is verified by simulation of the model in SPICE and by experimental measurement. The results show that the proposed model can simulate the electrical characteristics, including crosstalk and impedance, of high-density and high-speed connectors with satisfactory accuracy. Based on the proposed modeling and CAD simulators, the design and analysis of complicated high-density and high-speed connectors can be executed accurately and effectively. Compared with other previous models, the proposed model can significantly improve the accuracy of simulation.