Thin-Film Thermoelectric Modules for Power Generation Using Focused Solar Light

We demonstrated the fabrication of thin-film thermoelectric generators and evaluated their generation properties using solar light as a thermal source. Thin-film elements of Bi_0.5Sb_1.5Te₃ (p-type) and Bi₂Te_2.7Se_0.3 (n-type), which were patterned using the lift-off technique, were deposited on glass substrates using radiofrequency magnetron sputtering. After annealing at 300°C, the average Seebeck coefficients of p- and n-type films were 150???V/K and ?104???V/K, respectively, at 50°C to 75°C. A cylindrical lens was used to focus solar light to a line shape onto the hot side of the thin-film thermoelectric module with 15 p?Cn junctions. The minimum width of line-shaped solar light was 0.8?mm with solar concentration of 12.5 suns. We studied the properties of thermoelectric modules with different-sized p?Cn junctions on the hot side, and obtained maximum open voltage and power values of 140?mV and 0.7???W, respectively, for a module with 0.5-mm p?Cn junctions. The conversion efficiency was 8.75?×?10^?4%, which was approximately equal to the value estimated by the finite-element method.     

Electrochemically induced asymmetrical etching in InAlAs/InGaAs heterostructures for MODFET gate-groove fabrication

We have achieved a self-controlled asymmetrical etching in metalorganic chemical vapor deposition-grown InAlAs/InGaAs heterostructures, which can be suitable for fabricating modulation-doped field-effect transistors (MODFETs) with gate-groove profiles for improved performance. The technology is based on electrochemical etching phenomena, which can be effectively controlled by using different surface metals for ohmic electrodes. When surface metals of Pt and Ni are deposited on the source and the drain, respectively, the higher electrode potential of Pt results in slower etching on the source side than on the drain side. Thus, asymmetry of gate grooves can be formed by wet-chemical etching with citric-acid-based etchant. This represents a new possibility to conduct “recess engineering” for InAlAs/InGaAs MODFETs.     

Energy-level alignment at model interfaces of organic electroluminescent devices studied by UV photoemission: trend in the deviation from the traditional way of estimating the interfacial electronic structures

The electronic structures of model interfaces of organic electroluminescent (EL) devices were investigated with UV photoemission spectroscopy (UPS). Interfaces of TTN (tetrathianaphthacene) and TCNQ (tetracyanoquinodimethane) were also studied as extreme cases for hole transport and electron transport material, respectively. For all organic/metal interfaces studied, the work function of metal electrode was changed by deposition of organic layer, i.e., the vacuum level was shifted at the interface, indicating the invalidity of the traditional energy level alignment model where a common vacuum level was assumed at organic/metal interface. At TCNQ/Au, DP-NTCI/Al, which are acceptor/metal interfaces, upward shift of the vacuum level of organic layer relative to that of metal was observed, suggesting the formation of interfacial dipole due to electron-transfer from metal to acceptor. At other organic/metal interfaces, TPD(N, N'-diphenyl-N, N'-(3-methylphenyl)-1, 1'-biphenyl-4, 4'-diamine)/Au or ITO (indium tin oxide), ALq/sub 3/ (tris(8-hydroxyquinolino) aluminum)/Al, DP-NTCl(N, N'-diphenyl-1,4,5,8- naphthyltetracarboxylimide)/Al or Au, downward shift of the vacuum level was observed. Such downward shift has been also observed in our previous study for porphyrin/metal interfaces, and seems to be a trend for organic/metal interfaces at which no electron-transfer from metal to organic layer occurs. This trend suggests that the traditional model tends to underestimate (overestimate) the barrier height for hole (electron) injection. On the other hand, the vacuum level shift at ALq/sub 3//TPD interface was less than 0.1 eV, leading to an apparent applicability of the traditional model. However, it is not always the case for organic/organic interfaces: finite shift of 0.2 eV was observed at TTN/TCNQ interface due to electron-transfer from TTN to TCNQ. Possible origins of vacuum level shift at organic/metal interfaces were also discussed.     

Rain Attenuation at Millimeter Wavelength of 1.33 mm

Specific rain attenuation values calculated by using the four empirical raindrop-size distributions, that is, the Marshall and Palmer, the Joss, Thams and Walgvogel, the Ihara, Furuhama and Manabe, and the Weibull raindrop-size distributions. The millimeter wave measurement at 225 GHz (1.33mm) was compared with our calculations. It has been shown that the Weibull distribution has the best agreement with the measurements.     

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/sone-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter ζω_n (ζ is a damping factor and ω_n is the natural angular frequency of the PLL), and that the optimization focusing on the ω_n dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-μm Si bipolar technology (f_T = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers)     

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

Extraction of a plasma time-activity curve from dynamic brain PET images based on independent component analysis

A compartment model has been used for kinetic analysis of dynamic positron emission tomography (PET) data [e.g., 2-deoxy-2-18F-fluoro-D-glucose (FDG)]. The input function of the model [the plasma time-activity curve (pTAC)] was obtained by serial arterial blood sampling. It is of clinical interest to develop a method for PET studies that estimates the pTAC without needing serial arterial blood sampling. For this purpose, we propose a new method to extract the pTAC from the dynamic brain PET images using a modified independent component analysis [extraction of the pTAC using independent component analysis (EPICA). Source codes of EPICA are freely available at http://www5f.biglobe.ne.jp/?kimura/Software/top.html]. EPICA performs the appropriate preprocessing and independent component analysis (ICA) using an objective function that takes the various properties of the pTAC into account. After validation of EPICA by computer simulation, EPICA was applied to human brain FDG-PET studies. The results imply that the EPICA-estimated pTAC was similar to the actual measured pTAC, and that the estimated blood volume image was highly correlated with the blood volume image measured using 15O-CO inhalation. These results demonstrated that EPICA is useful for extracting the pTAC from dynamic PET images without the necessity of serial arterial blood sampling.     

A +10-dBm IIP/sub 3/ SiGe mixer with IM/sub 3/ cancellation technique

A third-order intermodulation (IM/sub 3/) cancellation technique using a submixer is proposed for a low-power low-distortion mixer. The IM/sub 3/ cancellation is achieved by summing IM/sub 3/ generated in a main mixer and the submixer, which are almost the same amplitude and opposite phase. The mixer was designed to operate at 870 MHz. The proposed technique reduces IM/sub 3/ by 18 dB with a current increase of about 15% and is suitable for low-power applications. The mixer achieved an input-referred third-order intercept point (IIP/sub 3/) of 10 dBm, a gain of 8.7 dB, and an NF of 9.8 dB and dissipates 30 mW from 2.9 V. The IC is fabricated in a SiGe bipolar transistor with f/sub T/= 30 GHz. The IC occupies 1.44 mm/spl times/1.44 mm.     

Design and characteristics of InGaAs/InP composite-channel HFET's

A design for composite-channel structures consisting of an InGaAs channel and an InP subchannel for use as heterostructure field-effect transistors is presented for the first time. This novel channel structure takes advantage of both the high drift velocity and low impact ionization of InP at high electric fields as well as the high electron mobility of InGaAs at low electric fields. It is shown that the doping density of the InP subchannel is the key parameter to realize the advantages of the composite channel. A very high transconductance of 1.29 S/mm and a current gain cutoff frequency of 68.7 GHz are achieved with 0.6 and 0.7 /spl mu/m gates, respectively. The average velocity of electrons in the composite channel is 2.9/spl times/10/sup 7/ cm/s. The devices have no kink phenomena in their I-V characteristics possibly due to low impact ionization in the InP subchannel.<>