Unified equation of state based on the lattice fluid theory for phase equilibria of complex mixtures part I. Molecular thermodynamic framework

Consistent calculation of fugacities of fluid mixtures remains as one of the most important subjects in contemporary molecular thermodynamics. In practice, equations of state (EOSs) and g^E-models have been used. However, most EOSs are erroneous for condensed phases at high densities and g^E-models are inapplicable for pressuresensitive systems. Recently to remedy the shortcomings in both approaches, there has been a surge of new g^E-EOS mixing rules. By equating any set of EOS and g^E-models, the limitations in both approaches could be resolved significantly. However, the self-consistency in the underlying concept of those mixing rules remains controversial. During the last several years, the present authors proposed a new lattice-fluid EOS and its simplification relevant to phase equilibrium calculations. Without employing any g^E-EOS mixing rule and with only two parameters for a pure component and one adjustable interaction energy parameter for a binary mixture, results obtained to date demonstrated that the EOSs are quantitatively applicable to a great variety of phase equilibrium properties of mixtures, especially, for complex and/or macromolecular systems. In the present article we summarize the EOSs and extended the applications to liquid-liquid Equilibria. In part I, we discussed briefly the molecular thermodynamic aspects of general derivation of the EOS and a brief discussion of applying the EOSs to pure fluids while the illustrative application to various real mixture systems is discussed in part II.     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

The effect of verbal elaborations on memory in young and older adults

The Stein paradigm was used to examine the circumstances under which verbal elaborations enhance memory in young and older adults. Subjects studied target adjectives that were embedded in one of three sentence contexts that varied in elaboration of the subject-adjective relationship: (1) nonelaborated base sentences; (2) base sentences with semantically consistent, but arbitrary verbal, elaborations; and (3) base sentences with explanatory verbal elaborations that clarified the significance of the subject-adjective relationship. The presence of the elaborations was varied at encoding and retrieval, and cued recall of the target adjectives was tested with incidental and intentional learning procedures. In Experiments 1A and 1B, explanatory elaborations at encoding and retrieval yielded the largest memorial facilitation for both young and older adults, and the benefit was comparable for the incidental and intentional learning measures. In Experiment 2, age-related differences in recall were minimal with explanatory elaborations at encoding and retrieval, but larger age differences occurred in the nonelaborated comparison conditions. In Experiment 3, explanatory elaborations present at encoding but not at retrieval enhanced recall when the original Stein stimuli were used, but not with the present stimuli. The implications of these results with regard to the mnemonic efficacy of verbal elaborations for young and older adults are discussed.     

Modified atmosphere packaging of a mixed prepared vegetable salad dish

The aim of this study was to design a modified atmosphere package for a mixed vegetable salad consisting of 75 g of cut carrot, 55 g of cut cucumber, 20 g of sliced garlic and 50 g of whole green pepper. Respiration data of all the components were combined with film permeability data to predict package atmospheres and design optimal packages for experimental testing for improved shelf-life of the produce. The optimal package avoided minimum O₂ and maximum CO₂ tolerance limits, and chilling injury temperatures for any component. A pouch form package made of 27 mm low density polyethylene developed a modified atmosphere of 2.0–2.1% O₂ and 5.5–5.7% CO₂, which was beneficial for all components and provided better quality retention than other test packages.     

A neural network-based power system stabilizer using power flowcharacteristics

A neural network-based power system stabilizer (neuro-PSS) is designed for a generator connected to a multi-machine power system utilizing the nonlinear power flow dynamics. The use of power flow dynamics provides a PSS for a wide range of operation with reduced size neural networks. The neuro-PSS consists of two neural networks: neuro-identifier and neuro-controller. The low-frequency oscillation is modeled by the neuro-identifier using the power flow dynamics, then a generalized backpropagation-through-time (GBTT) algorithm is developed to train the neuro-controller. The simulation results show that the neuro-PSS designed in this paper performs well with good damping in a wide operation range compared with the conventional PSS     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.