Intra-level voltage ramping-up to dielectric breakdown failure on Cu/porous low-k interconnections in 45 nm ULSI generation

The degradation of reliability for intra-level voltage-breakdown in the 45 nm generation node has become an increasingly important issue with the introduction of porous low-k dielectrics. The dominant failure mechanism for lower voltage ramping-up to dielectric breakdown and higher leakage current was that more electrons easily transported through the percolation path in intra-level porous low-k interconnections damaged from HF corrosion. An optimal ultraviolet curing process and a less NH₃ plasma pre-treatment on porous low-k dielectrics before the SiCN capping layer are developed to improve performance in both of these cases. The stiff configuration of the reconstruction of Si-O network structures and less HF corrosion is expected to have high tolerance to electrical failure. As a result, the proposed model of this failure facilitates the understanding of the reliability issue for Cu/porous low-k interconnections in back-end of line (BEOL) beyond 45 nm nodes.     

A novel Al and Y codoped ZnO/n-Si heterojunction solar cells fabricated by pulsed laser deposition

Al and Y codoped ZnO (AZOY) transparent conducting oxide (TCO) thin films were first deposited on n-Si substrates by pulsed laser deposition (PLD) to form AZOY/n-Si heterojunction solar cells. However, the properties of the AZOY emitter layers are critical to the performance of AZOY/n-Si heterojunction solar cells. To estimate the properties of AZOY thin films, films deposited on glass substrates with various substrate temperatures (T_s) were analyzed. Based on the experimental results, optimal electrical properties (resistivity of 2.8 ± 0.14 × 10^?4 Ω cm, carrier mobility of 27.5 ± 0.55 cm²/Vs, and carrier concentration of 8.0 ± 0.24 × 10²⁰ cm^?3) of the AZOY thin films can be achieved at a T_s of 400 °C, and a high optical transmittance of AZOY is estimated to be >80% (with glass substrate) in the visible region under the same T_s. For the AZOY/n-Si heterojunction solar cells, the AZOY thin films acted not only as an emitter layer material, but also as an anti-reflected coating thin film. Thus, a notably high short-circuit current density (J_sc) of 31.51 ± 0.186 mA/cm² was achieved for the AZOY/n-Si heterojunction solar cells. Under an AM1.5 illumination condition, the conversion efficiency of the cells is estimated at only approximately 4% (a very low open-circuit voltage (V_oc) of 0.24 ± 0.001 V and a fill factor (FF) of 0.51 ± 0.011) without any optimization of the device structure.     

High efficiency a-Si:H/a-Si:H solar cell with a tunnel recombination junction and a n-type μc-Si:H layer

In this paper, a-Si:H/a-Si:H tandem solar cells have been fabricated using a plasma enhanced chemical vapor deposition. The solar cell has a structure of glass/textured-SnO₂/p-a-SiC:H/i-a-Si:H/n-μc-Si:H/p-μc-Si:H/p-a-SiC:H/i-a-Si:H/n-μc-Si:H/gallium-doped zinc oxide/Ag. Higher efficiency in a-Si:H/a-Si:H tandem solar cells can be achieved by use of a good tunnel recombination junction (TRJ) and current matching. Accordingly, solar cells with a n-μc-Si:H/p-μc-Si:H TRJ are investigated. This paper studies the influence of the thickness of the top intrinsic amorphous silicon (i-a-Si:H) layer with regard to short circuit current density and current matching between the top and the bottom cells. Experimental results with lab-fabricated samples show that the optimal thickness of the i-a-Si:H layer in the top and bottom cells is 60 and 250 nm, respectively. An initial conversion efficiency of 10.29% is achieved for the optimized a-Si:H/a-Si:H tandem solar cell. Light-induced degradation of the solar cells is about 17%.     

Effect of process parameters on the growth and properties of impurity-doped zinc oxide transparent conducting thin films by RF magnetron sputtering

Zinc oxide transparent conducting thin films co-doped with aluminum and ruthenium were grown on polyethylene terephthalate substrates at room temperature using RF magnetron sputtering. The crystal growth and physical properties of the films were investigated with respect to the variation of discharge power density from 1.5 to 6.1 W/cm² and sputtering pressure from 0.13 to 2.0 Pa. X-ray diffraction (XRD) and field emission scanning electron microscopy (FESEM) showed that the films grown with 3.6 W/cm² power density and sputtering pressure of 0.4 Pa had the best crystallinity and larger pyramid-like grains. The optimized electrical resistivity had a lowest measured value of about 9 × 10⁻⁴ Ω cm. The low carrier mobilities of the films (3-8.9 cm² V⁻¹ s⁻¹) have been discussed in terms of what is believed to be the dominant effect of ionized impurity scattering, but in addition chemisorption of oxygen on the film surface and effect of grain boundaries are also thought to be significant. The transmittances of the films in the visible range are greater than 80%, while the optical band gaps are in the order of 3.337-3.382 eV.     

A fully matched high linearity 2-W PHEMT MMIC power amplifier for 3.5 GHz applications

A 2-W monolithic microwave integrated circuit power amplifier, operating between 3.3 and 3.8GHz by implementing AlGaAs/InGaAs/GaAs pseudomorphic high electronic mobility transistor for the applications of wideband code division multiple access, wireless local loop, and multichannel multipoint distribution service, is demonstrated. This two-stage amplifier is designed to fully match 50/spl Omega/ input and output impedances. With a dual-bias configuration, the amplifier possesses the characteristics of 30.4dB small-signal gain and 34dBm 1-dB gain compression power with 37.1% power added efficiency. Moreover, with a single carrier output power level of 24dBm, high linearity with a 43.5-dBm third-order intercept point operating at 3.5GHz is also achieved.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Effects of inelastic scattering on interband tunneling inGaSb/AlSb/InAs/GaSb/AlSb/lnAs broken-gap interband tunneling structures

Effects of inelastic scattering on interband tunneling in GaSb/AlSb/InAs/GaSb/AlSb/InAs BGIT's are investigated. The broadening mechanisms due to inelastic scattering are incorporated into the interband tunneling theory. The transmission and reflection coefficients are calculated with the aid of a three-band model, in which the conduction, light-hole, and split-off bands are coupled with one another. It is found that the inelastic scattering lowers the transmission peak and broadens the full-width at half-maximum, resulting in the decrease of the tunneling current. The calculated tunneling current due to inelastic scattering is found to have better agreement with the experiments. In addition, as the valley current plays an important role in the peak-to-valley current ratio (PVR), we then try to deduce the origin of the valley currents. The thermionic current is included in the valley current to estimate the peak-to-valley current ratio. The thermionic component from the GaSb well has important contribution to the valley current in the studied structures. The peak-to-valley current ratio is also estimated and found to have better agreement with the experiment when the inelastic scattering is considered     

Improving the characteristics of CdS and CIAS films and the performances of CIAS solar cells by electrodeposition Cu–Se/CIAS binary structure precursors on FTO substrate

Cu-poor electrodeposited CuIn_1?xAl_xSe₂ (CIAS) precursor films were prepared to investigate the alteration in surface morphology of post-annealed CIAS films through post-annealing temperature adjustment. Scanning electron microscopy (SEM) and atomic force microscope (AFM) analyses demonstrated that surface morphology and root–mean–square (RMS) roughness of post-annealed CIAS films exhibited uneven and rough triangular structures. The crystal size of post-annealed CIAS films can be increased by increasing post-annealing temperature. The precursor film structure was modified by substituting Cu–Se/CIAS binary structure with CIAS single structure to proceed with the investigation. The apparent variation in surface morphology of post-annealed CIAS films changed from rough triangular structures to smooth round structures, and the RMS roughness of post-annealed CIAS films was reduced to <100 nm. The reduction was attributed to the formation of Cu–Se liquid phases during the post-annealing process, which enhanced elemental migration, recombination, and promotion of large grains and smooth surface formation. X-ray diffraction patterns showed three preferred growth orientations along the (112), (204/220), and (116/312) planes with chalcopyrite structures for all species. In addition, the characteristics of surface morphology, RMS roughness, and current measurement of subsequently deposited cadmium sulfide (CdS) film were studied and examined via SEM and AFM analyses. The surface morphology of CdS films deposited on binary structure post-annealed CIAS films exhibited smoothness, compactness, small RMS roughness, and large crystals with round and film-like structure. The AFM current images indicated that the distribution of leakage current paths was greatly diminished by changing the precursor film structure from CIAS single structure to Cu–Se/CIAS binary structure. The dark current–voltage characteristics of the CdS/CIAS heterojunctions showed that the reverse dark current density was decreased by approximately one order of magnitude from 4.02 × 10^?4 (single structure) to 4.26 × 10^?5 A/cm² (binary structure). Furthermore, the conversion efficiency of CIAS solar cells was enhanced from 0.52 (single structure) to 1.44 % (binary structure) with increase in V_oc and J_sc.     

A planarized shallow-trench-isolation for GaAs devices fabricationusing liquid phase chemical enhanced oxidation process

A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFETs fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated     

Titanium nitride as spreading layers for AlGaInP visible LEDs

Thin titanium nitride (TiN) films with low sheet resistance and high transparency were deposited on AlGaInP light-emitting diodes (LEDs) to improve light extraction from the LED surface. Comparison test devices were fabricated both with and without TiN spreading layers. Results show LED current crowding at high current is reduced for devices with TiN current spreading film, improving external efficiency. It is confirmed that TiN films are feasible as current spreading layers of AlGaInP LEDs.