DNA Computing Boosted by a Cationic Copolymer

The huge information storage capability of DNA and its ability to self‐assemble can be harnessed to enable massively parallel computing in a small space. DNA‐based logic gates are designed that rely on DNA strand displacement reactions; however, computation is slow due to time‐consuming DNA reassembly processes and prone to failure as DNA is susceptible to degradation by nucleases and under certain solution conditions. Here, it is shown that the presence of a cationic copolymer boosts the speed of DNA logic gate operations that involve multiple and parallel strand displacement reactions. Two kinds of DNA molecular operations, one based on a translator gate and one on a seesaw gate, are successfully enhanced by the copolymer without tuning of computing conditions or DNA sequences. The copolymer markedly reduces operation times from hours to minutes. Moreover, the copolymer enhances nuclease resistance.     

Growth of (111) HgCdTe on (100) Si by MOVPE using metalorganic tellurium adsorption and annealing

(lll)B CdTe layers free of antiphase domains and twins were directly grown on (100) Si 4°-misoriented toward<011> substrates, using a metalorganic tellurium (Te) adsorption and annealing technique. Direct growth of (lll)B CdTe on (100) Si has three major problems: the etching of Si by Te, antiphase domains, and twinning. Te adsorption at low temperature avoids the etching effect and annealing at a high temperature grows single domain CdTe layers. Te atoms on the Si surface are arranged in two stable positions, depending on annealing temperatures. We evaluated the characteristics of (lll)B CdTe and (lll)B HgCdTe layers. The full width at half maximum (FWHM) of the x-ray double crystal rocking curve (DCRC) showed 146 arc sec at the 8 |im thick CdTe layers. In Hg_1−xCd_xJe (x = 0.22 to 0.24) layers, the FWHMs of the DCRCs were 127 arc sec for a 7 (im thick layer and 119 arc sec for a 17 (im thick layer. The etch pit densities of the HgCdTe were 2.3 x 106 cm2 at 7 ^m and 1.5 x 106 cm-2 at 17 um.     

High-power CW-DFB laser diode modules for CATV applications operating at 1550 nm

Investigation of the correlation between longitudinal photon density distribution and spectral linewidth re-broadening, in conjunction with carefully designed coupling optics, enable laser modules that simultaneously achieve very high fibre-coupled power of 175 mW and very narrow linewidth<1 MHz even at /spl sim/120 mW of output power to be successfully fabricated.     

Metallic Nanowire Coupled CsPbBr3 Quantum Dots Plasmonic Nanolaser

Plasmonic nanolasers provide a valuable opportunity for expanding sub-wavelength applications. Due to the potential of on-chip integration, semiconductor nanowire (NW)-based plasmonic nanolasers that support the waveguide mode attract a high level of interest. To date, perovskite quantum dots (QDs) based plasmonic lasers, especially nanolasers that support plasmonic-waveguide mode, are still a challenge and remain unexplored. Here, metallic NW coupled CsPbBr₃ QDs plasmonic-waveguide lasers are reported. By embedding Ag NWs in QDs film, an evolution from amplified spontaneous emission with a full width at half maximum (FWHM) of 6.6 nm to localized surface plasmon resonance (LSPR) supported random lasing is observed. When the pump light is focused on a single Ag NW, a QD-NW coupled plasmonic-waveguide laser with a much narrower emission peak (FWHM = 0.4 nm) is realized on a single Ag NW with the uniform polyvinylpyrrolidone layer. The QDs serve as the gain medium while the Ag NW serves as a resonant cavity and propagating plasmonic lasing modes. Furthermore, by pumping two Ag NWs with different directions, a dual-wavelength lasing switch is realized. The demonstration of metallic NW coupled QDs plasmonic nanolaser would provide an alternative approach for ultrasmall light sources as well as fundamental studies of light matter interactions.     

A high-speed halftoning processor for raster scanned images

A high-speed bilevel reproduction algorithm, called modified error diffusion (MED) algorithm, has been developed to provide high-quality halftoning images for continuous tone images and has been implemented in a CMOS LSI chip. The chip has been designed with standard-cell 1.5-μm CMOS technology using an optimum layout design. The chip has achieved a maximum processing speed of 60 ns/pixel     

Phase and magnetic properties of iron oxide clusters in 20CaO·20SiO2·7Fe2O3·6FeO glasses

The annealing of 20CaO·20SiO₂·7Fe₂O₃·6FeO glasses at 973K in vacuo produced clusters of iron oxide, the shape of which was nearly spherical and the diameter distributed in the narrow range 25–115Å. The phase of clusters was identified to be Fe³⁺(Fe³⁺ _{poststagger|1.30}Fe²⁺ _{poststagger|0.55}V_0.15)·O₄ in the inverse spinel structure based upon the Mössbauer spectra and x-ray diffraction profiles. The clusters exhibited superparamagnetism and their effective anisotropy energy constant was inversely proportional to the cluster diameter. The magnetization of the glasses measured by a vibrating sample magnetometer was 7.2 × 10^-6 Wbmkg^-1 at 10 kOe at room temperature and smaller than the value calculated assuming that the whole clusters have superparamagnetism. These results suggest the pinning of spins near the cluster surface.     

Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I–V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10–40 GHz showed the conductance modulation by drain–source voltage. These results indicate the existence of plasma wave interactions.     

Advanced CD Control Technology for 65-nm Node Dual Damascene Process

This paper describes an advanced critical dimension (CD) control technology for a 65-nm node dual damascene process and beyond. A newly developed deposition enhanced shrink etching (DESE) process was introduced into both via and trench etching. This technology realizes not only dynamic via shrink ranging 40 nm but also accurate trench CD control by feedforward technology. Etching performance was investigated by electrical results of 65-nm Cu/low-k interconnects using porous chemical-vapor deposition SiOC. The 100% yields of 60-M via chains verified the DESE process robustness.     

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.