Genetic evolutionary algorithm for optimal allocation of wavelength converters in WDM optical networks

In this article, a genetic evolutionary algorithm is proposed for efficient allocation of wavelength converters in WDM optical networks. Since wavelength converters are expensive, it is desirable that each node in WDM optical networks uses a minimum number of wavelength converters to achieve a near-ideal performance. The searching capability of genetic evolutionary algorithm has been exploited for this purpose. The distinguished feature of the proposed approach lies in handling the conflicting circumstances during allocation of wavelength converters considering various practical aspects (e.g., spatial problem, connectivity of a node with other nodes) rather than arbitrarily to possibly improve the overall blocking performance of WDM optical networks. The proposed algorithm is compared with a previous approach to establish its effectiveness and the results demonstrate the ability of the proposed algorithm to efficiently solve the problem of Optimal Wavelength Converters Allocation (OWCA) in practical WDM optical networks.

Simulation, modeling, and crystal growth of Cd0.9Zn0.1Te for nuclear spectrometers

High-quality, large (10 cm long and 2.5 cm diameter), nuclear spectrometer grade Cd_0.9Zn_0.1Te (CZT) single crystals have been grown by a controlled vertical Bridgman technique using in-house zone refined precursor materials (Cd, Zn, and Te). A state-of-the-art computer model, multizone adaptive scheme for transport and phase-change processes (MASTRAP), is used to model heat and mass transfer in the Bridgman growth system and to predict the stress distribution in the as-grown CZT crystal and optimize the thermal profile. The model accounts for heat transfer in the multiphase system, convection in the melt, and interface dynamics. The grown semi-insulating (SI) CZT crystals have demonstrated promising results for high-resolution room-temperature radiation detectors due to their high dark resistivity (ρ≈2.8 × 10¹¹ Θ cm), good charge-transport properties [electron and hole mobility-life-time product, μτ_e≈(2–5)×10⁻³ and μτ_h≈(3–5)×10⁻⁵ respectively, and low cost of production. Spectroscopic ellipsometry and optical transmission measurements were carried out on the grown CZT crystals using two-modulator generalized ellipsometry (2-MGE). The refractive index n and extinction coefficient k were determined by mathematically eliminating the ∼3-nm surface roughness layer. Nuclear detection measurements on the single-element CZT detectors with ²⁴¹Am and ¹³⁷Cs clearly detected 59.6 and 662 keV energies with energy resolution (FWHM) of 2.4 keV (4.0%) and 9.2 keV (1.4%), respectively.     

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)     

Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies

Dual-V_t design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-V_t devices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-V_t devices, which in the worst case can increase the total leakage in dual-V_t design. Moreover, process parameter variations (and in turn V_t variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-V_t design methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-V_t design can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-V_t design, while ensuring target yield. This paper also shows that nonscalability of the present way of realizing high-V_t devices results in negligible power savings beyond 25-nm technology. Hence, different dual-V_t process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-V_t designs in future technologies.     

Tomographic fluorescence imaging in tissue phantoms: a novel reconstruction algorithm and imaging geometry

A novel image reconstruction algorithm has been developed and demonstrated for fluorescence-enhanced frequency-domain photon migration (FDPM) tomography from measurements of area illumination with modulated excitation light and area collection of emitted fluorescence light using a gain modulated image-intensified charge-coupled device (ICCD) camera. The image reconstruction problem was formulated as a nonlinear least-squares-type simple bounds constrained optimization problem based upon the penalty/modified barrier function (PMBF) method and the coupled diffusion equations. The simple bounds constraints are included in the objective function of the PMBF method and the gradient-based truncated Newton method with trust region is used to minimize the function for the large-scale problem (39919 unknowns, 2973 measurements). Three-dimensional (3-D) images of fluorescence absorption coefficients were reconstructed using the algorithm from experimental reflectance measurements under conditions of perfect and imperfect distribution of fluorophore within a single target. To our knowledge, this is the first time that targets have been reconstructed in three-dimensions from reflectance measurements with a clinically relevant phantom.     

Discrete Rayleigh distribution

Using a general approach for discretization of continuous life distributions in the univariate & bivariate situations, we have proposed a discrete Rayleigh distribution. This distribution has been examined in detail with respect to two measures of failure rate. Characterization results have also been studied to establish a direct link between the discrete Rayleigh distribution, and its continuous counterpart. This discretization approach not only expands the scope of reliability modeling, but also provides a method for approximating probability integrals arising out of a continuous setting. As an example, the reliability value of a complex system has been approximated. This discrete approximation in a nonnormal setting can be of practical use & importance, as it can replace the much relied upon simulation method. While the replication required is minimal, the degree of accuracy remains reasonable for our suggested method when compared with the simulation method.     

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current

Wavelet transform has the property of resolving signal in both time and frequency unlike Fourier transform. In this work, we show that time-domain information obtained from wavelet analysis of supply current can be used to test the frequency specification of analog filters efficiently. The pole/zero locations in the frequency response of analog filters shift due to change in component values with process variations. It is essential to test the filters for the shift in frequency response and fix it during production test. Wavelet analysis of supply current can be a promising alternative to test frequency specification of analog filters, since it needs only one AC stimulus and is virtually unaffected by transistor threshold variation. Simulation results on two test circuits demonstrate that we can estimate pole/zero shift with less than 3% error using only one measurement, which requires about 18 measurements in the conventional technique.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA. He has worked in the EDA industry on RTL synthesis and verification for about three years. His research interest includes design methodologies for high-performance low-power testable VLSI system, defect-based testing, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN, USA. He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

Parallel interference cancellation for uplink multirate overlay CDMA channels

To provide new and/or higher rate wireless services with limited spectrum resources, frequency overlay has been naturally proposed to accommodate the new and legacy systems in a common band. We address the multiuser detection problem for overlaid code-division multiple-access (CDMA) scenarios. However, in contrast to the well-studied conventional single-rate CDMA, miscellaneous systems overlay almost always indicates the presence of multirate traffic that introduces an additional degree of freedom in receiver design-i.e., differences in the symbol rates. We concentrate on receiver design for multirate traffic, while assuming a lack of information exchange between the constituent (new and legacy) systems, as is commonplace in practice. We propose a receiver architecture based on linear parallel interference cancellation where the out-of-rate intersystem interference is estimated and subtracted by means of its characteristic subspace, thereby avoiding the need for the exact knowledge of signature waveforms of the interfering system. Simulation results validate our solution and show that the proposed receiver has better performance in various aspects than several other solutions for the same purpose.     

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.