Texture analysis and classification with tree-structured wavelettransform

A multiresolution approach based on a modified wavelet transform called the tree-structured wavelet transform or wavelet packets is proposed. The development of this transform is motivated by the observation that a large class of natural textures can be modeled as quasi-periodic signals whose dominant frequencies are located in the middle frequency channels. With the transform, it is possible to zoom into any desired frequency channels for further decomposition. In contrast, the conventional pyramid-structured wavelet transform performs further decomposition in low-frequency channels. A progressive texture classification algorithm which is not only computationally attractive but also has excellent performance is developed. The performance of the present method is compared with that of several other methods.     

A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit

A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder     

Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states

An analytical drain current model for a-Si:H TFTs obtained by considering deep and tail states simultaneously is presented. Using an effective temperature approach, the localised deep and tail states have been considered in the DC model such that no approximations are needed. As verified by the published data, this analytical DC model provides an accurate prediction of the drain current characteristics of an a-Si:H thin film transistor.<>     

Design and analysis of defect tolerant hierarchical sortingnetworks

A hierarchical modular sorting network which achieves a balance in area-time cost between the odd-even transposition sort and the bitonic sort is presented. It consumes less hardware than a single-level odd-even sorter and reduces the wire complexity of the bitonic sorter in VLSI or WSI (wafer-scale integration) implementation. The optimal number of levels in the hierarchy is evaluated, and the sorting capability of each level is derived so as to minimize the hardware overhead. The hierarchical sorting network is very regular in structure and hence defect tolerance capability can be included more easily than in any existing sorting network with the same time complexity. Redundancy is provided at every level of the hierarchy. Hierarchical reconfiguration is performed by replacing the defective cells at the bottom level with the spare cells first and repeating the process at the next higher level if there is not enough redundancy at the current level. Yield analysis is performed to demonstrate the effectiveness of the approach     

国内外越野车辆模块化独立悬架技术发展现状

梳理了国内外模块化独立悬架的理论研究及应用现状,分析了模块化独立悬架的特点及优势,认为加快推动该技术领域的深入研究,对提升我军陆基装备的越野机动性能具有十分重要的意义.     

Study of the numerical simulation of tight sandstone gas molecular diffusion based on digital core technology

Diffusion is an important mass transfer mode of tight sandstone gas. Since nano-pores are extensively developed in the interior of tight sandstone, a considerable body of research indicates that the type of diffusion is mainly molecular diffusion based on Fick’s law. However, accurate modeling and understanding the physics of gas transport phenomena in nanoporous media is still a challenge for researchers and traditional investigation (analytical and experimental methods) have many limitations in studying the generic behavior. In this paper, we used Nano-CT to observe the pore structures of samples of the tight sandstone of western of Sichuan. Combined with advanced image processing technology, threedimensional distributions of the nanometer-sized pores were reconstructed and a tight sandstone digital core model was built, as well the pore structure parameters were analyzed quantitatively. Based on the digital core model, the diffusion process of methane molecules from a higher concentration area to a lower concentration area was simulated by a finite volume method. Finally, the reservoir’s concentration evolution was visualized and the intrinsic molecular diffusivity tensor which reflects the diffusion capabilities of this rock was calculated. Through comparisons, we found that our calculated result was in good agreement with other empirical results. This study provides a new research method for tight sandstone digital rock physics. It is a foundation for future tight sandstone gas percolation theory and numerical simulation research.     

Adaptive control of arterial blood pressure with a learningcontroller based on multilayer neural networks

The authors discuss a two-model multilayer neural network controller for adaptive control of mean arterial blood pressure (MABP) using sodium nitroprusside. A model with an autoregressive moving average (ARMA), representing the dynamics of the system, and a modified backpropagation training algorithm are used to design the control system to meet specified objectives of design (settling time and undershoot/overshoot) and clinical constraints. The controller is associated with a weighting-determinant unit (WDU) to determine and update the output weighting factor of the parallel two-model neural network for adequate control action and a control-signal modification unit (CMU) to comply with clinical constraints and to suppress the effect of adverse noise and to improve the WDU performance. Extensive computer simulations indicate satisfactory performance and robustness of the proposed controller in the presence of much noise, over the full range of plant parameters, uncertainties, and large variations of parameters     

Quasi-saturation capacitance behavior of a DMOS device

This paper reports a simulation study on the capacitance characteristics of a double-diffused metal-oxide semiconductor (DMOS) device operating in the quasi-saturation region. From the analysis, the capacitance effect of the gate oxide upon the drift region cannot be modeled as an overlap capacitance, because the drain-gate/source-gate capacitances of the DMOS device may exceed the gate-oxide capacitance due to the larger voltage drop over the gate oxide than the change in the imposed gate bias when entering the quasi-saturation region. This effect can be the explanation for the plateau behavior in the gate charge plot during turn-on and turn-off of the DMOS device. Based on the small-signal equivalent capacitance model, the accumulated charge in the drift region below the gate oxide may thoroughly associate with the drain terminal in the prequasi-saturation region and with the source terminal in the quasi-saturation region     

A novel technique for profiling the lateral n- dopingconcentrations of submicron LDD MOS devices

This paper reports a simple I-V method for the first time to determine the lateral lightly-doped source/drain (S/D) profiles (n^- region) of LDD n-MOSFETs. One interesting result is the direct observation of the reverse-short-channel effect (RSCE). It is observed that S/D n^- doping profile is channel length dependent if reverse short-channel effect exists as a result of the interstitial imperfections caused by Oxide Enhanced Diffusion (OED) or S/D implant. Not only the lateral profiles for long-channel devices but also for short-channel devices can be determined. One other practical application of the present method for device drain engineering has been demonstrated with a LATID MOS device drain engineering work. It is convincible that the proposed method is well suited for the characterization and optimization of submicron and deep-submicron MOSFETs in the current ULSI technology     

A 1.5-V full-swing bootstrapped CMOS large capacitive-load drivercircuit suitable for low-voltage CMOS VLSI

This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous