Energy savings in chemical plants: a vinyl chloride case history

To optimise the energy utilisation in the processes (and in particular in the chemical industry) it is useful to identify (when possible) process configurations in which the driving forces are uniform and the entropy generation approaches zero when the size of the plant increases. Such ideal configurations can be used as references and, to obtain practical plant flow diagrams, they have to be modified, according to the peculiar features of the process and the plant, the economical factors and the safety and environmental requirements. This paper presents, after a short methodological introduction, a vinyl chloride plant optimisation, based on such concepts and realised in the Porto Torres plant by the European Vinyl Corporation. Vinyl chloride monomer (VCM) is obtained by ethylene dichloride (EDC) cracking; furnace effluents containing VCM, EDC, hydrogen chloride (HCl) and chlorinated byproducts are processed through quench towers and a distillation train in order to separate the various components. The key of the new technology is the distillation sequence, which is adjusted to make it similar to the thermodynamically optimal configuration. Due to the new temperature levels of reboilers and condensers, a better heat cascading and a reduction of the steam consumption are obtained. The modification of the existing plant with a nominal capacity of 150,000 t/a has been realised using mainly the existing columns and exchangers; a HCl distillation column and three heat exchangers have been added; a new screw compressor allows the use of the existing cooling system. In a 10-day test run carried out at 50% capacity after the modification of the plant a reduction of the steam consumption of 50% was achieved.     

Effect of free-SH containing compounds on allyl isothiocyanate antimicrobial activity against Escherichia coli O157:H7

ABSTRACT:  Escherichia coli O157:H7 contamination is a significant meat safety issue in many countries. Allyl isothiocyanate (AIT) is a natural compound found to limit the survival of E. coli O157:H7 and other pathogens in meat and meat products. In the present study, it was found that glutathione and cysteine naturally present in meat can interfere with AIT antimicrobial activity. Spectroscopy, HPLC, and LC-MS were used to confirm that glutathione was able to react with AIT and formed a conjugate with no or low bactericidal activity against the tested organisms. The same reaction also occurred at pH values of 4.9 and 5.8 at 25 and 4 °C, respectively, which broadly represent storage conditions in raw beef (pH 5.8) and during fermented sausage (pH 4.9) manufacture. Reactions observed help to explain reduction in antimicrobial potency of AIT in food (meat) systems.     

A case study in computer-aided co-design of embedded controllers

We present an application of the methodology and of the various software tools embedded in the POLIS co-design system. The application is in the realm of automotive electronics: a shock absorber controller, whose specification comes from an actual product. All aspects of the design process are closely examined, including high level language specification and automatic hardware and software synthesis. We analyze different software implementation styles, compare the results, and outline the future developments of our work.This work was partially supported by SRC Contract DC-324-028 and by MURST Research Project VLSI Architectures.     

Optimizing transistor networks using a graph-based technique

Currently, most integrated circuits have higher density of transistors on the small physical area, reduced power consumption and greater performance. An important factor that has contributed for this is the representation of logic functions with a reduced number of transistors. While the generation of a series?Cparallel network can be straightforward once a minimized Boolean expression is available, this may not be an optimum solution. This paper proposes a graph-based solution for minimizing the number of transistors that compose a network by edges sharing. The algorithm starts from a sum-of-products expression and can achieve non-series-parallel arrangements. The Wheatstone bridge arrangements contribute for the transistor count reduction. Experimental results demonstrate the efficiency of the approach when comparing to traditional factorization algorithms implemented in the SIS software. When applying to the set of four input p-class logic functions, the proposed method presents advantages if compared to the good-factor algorithm.     

Power efficient SDS motion estimation architecture using dynamic iteration control and hierarchical adder compressors for real time HDTV video coding

This paper presents a high performance, power efficient and low hardware cost architecture for motion estimation (ME) targeting portable consumer applications. This hardware uses the Sub-sampled Diamond Search algorithm (SDS) with a Dynamic Iteration Control (DIC). The SDS–DIC algorithm can significantly reduce the number of SAD (Sum of Absolute Difference) calculations for block matching, thus enabling the development of an efficient hardware design for the ME. The DIC technique allows for the required throughput to be achieved with a restriction in the number of iterations, which contributes to the reduction in the overall number of clock cycles needed for the motion vector calculation. The processing units (PU) of the ME were developed by using efficient hierarchical adder-compressors, where simultaneous additions of more than two operands can be performed. The results we present show that, by using both the adder compressors in the PU and the DIC technique, it is possible to obtain an efficient ME architecture with higher performance and reduced power consumption. The architecture that implements this algorithm and the PUs was described in VHDL. Hardware synthesis results are presented for a 0.18 μm CMOS standard cell library. The architecture can reach real time for HDTV 1080p with less than 40 mW of power consumption.     

Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos

This article presents an architecture for the fractional motion estimation (FME) of the H.264/AVC video coding standard focusing in a good tradeoff between the hardware cost and the video quality. The support to FME guarantees a high quality in the motion estimation process. The applied algorithmic simplifications together with the multiplierless implementation and with a well balanced pipeline allow a low cost and a high throughput solution. The architecture was also designed to avoid redundant external memory accesses when computing the FME. The design was divided in two main modules: integer motion estimation (with diamond search algorithm) and fractional refinement (half-pixel and quarter-pixel interpolation and search). The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The architecture is able to reach 260 MHz when running in the target FPGA. In worst case scenario, this operation frequency allows a processing rate of 43 HD 1080p (1,920 × 1,080 pixels) frames per second, surpassing the requirements for real time processing. In comparison to related works, the developed architecture was able to achieve a good tradeoff among hardware costs, video quality and processing rate.     

Empirical comparison of MIMO and beamforming schemes for outdoor-indoor scenarios

We present an empirically based comparative study of spectral efficiency for a variety of transmission systems applicable to a fixed or repositionable wireless environment, in the context of Wi-Fi, WiMAX or MuniNet systems. A narrowband 4×4 Multiple Input Multiple Output (MIMO) channel sounder was constructed and a series of outdoor to indoor measurements were carried out, in multiple locations and with different array configurations. The channel measurements were used to compute the efficiency of different systems that could be deployed in such scenarios, ranging from a full MIMO system with perfect Channel State Information (CSI) at both ends to simple diversity schemes such as classical beamforming. We show comparisons of efficiency for the different transmit/receive configurations operating in a representative variety of locations. Our results indicate that for low values of signal to noise ratio (SNR), in the range of 5dB, such as found in strong interference scenarios, simple schemes can achieve median spectral efficiencies as high as 80% of that of MIMO with complete CSI.     

A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test

This paper describes a tester architecture for Accelerometer and Gyroscope Micro-ElectroMechanical System (MEMS) devices test and calibration, allowing increased parallelism rate and process accuracy. The proposed tester architecture tackles some critical issues related to MEMS testing, such as mitigating mechanical concerns that potentially impact on the equipment Mean Time Between Maintenance and guaranteeing a sufficient number of measurements in the time unit. The proposed strategy consists in an innovative and low cost tester resource partitioning that overcomes current limitations to multisite Accelerometer and Gyroscope MEMS testing. A tester prototype was implemented exploiting FPGAs; feasibility and effectiveness of the proposed methodology was demonstrated on commercial accelerometer and gyroscope MEMS devices.     

144 Channel measurement IC for CdZnTe sensors with energy and time resolution

A 144 channel measurement IC for CdZnTe detectors, used for PET, is presented. Each channel consists of a charge sensitive amplifier, a fast and a slow shaper, a peak sampler for the energy acquisition and an event detector based on a time to digital converter to generate an accurate time stamp for each event. The channels are multiplexed to a fast pipeline ADC on demand. Measurement results for the ASIC showed a noise equivalent input charge of 800 e⁻ rms and a time resolution of 737 ps rms. Evaluation results with a CdZnTe detector yielded an energy resolution of 4.4% full width half maximum at 662 keV with a ¹³⁷Cs radiation source. The IC is implemented on a 180 nm CMOS process with a total chip size of 100 mm².     

Polyphase FIR Networks Based on Frequency Sampling for Multirate DSP Applications

It is well known that the frequency sampling approach to the design of Finite Impulse Response digital filters allows recursive implementations which are computationally efficient when most of the frequency samples are integers, powers of 2 or null. The design and implementation of decimation (or interpolation) filters using this approach is studied herein. Firstly, a procedure is described which optimizes the tradeoff between the stopband energy and the deviation of the passband from the ideal filter. The search space is limited to a small number of samples (in the transition band), imposing the condition that the resulting filter have a large number of zeros in the stopband. Secondly, three different structures to implement the decimation (or interpolation) filter are proposed. The implementation complexity, i.e., the number of multiplications and additions per input sample, are derived for each structure. The results show that, without taking into account finite word-length effects, the most efficient implementation depends on the filter length to decimation (or interpolation) ratio.