Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

A fully soft-switched extended-period quasi-resonantpower-factor-correction circuit

This paper presents the design criteria, procedure, and implementation of a soft-switched power-factor-correction (PFC) circuit based on the extended-period quasi-resonant (EPQR) principles. All power electronic devices including switches and diodes in the circuit are fully soft switched. The design method is demonstrated in a prototype circuit. The operating principles are confirmed with computer simulation and experimental results. A comparison of the EP-QR operation and zero-voltage-transition (ZVT) pulse-width modulation (PWM) method     

Van vleck paramagnetism of the diluted intermetallic compounds Pr1−x Y x Ni5 at fields up to 15 T

We have measured the 16 Hz susceptibility of the diluted Van Vleck paramagnets Pr_1−x Y _x Ni₅ withx=0.00, 0.05, 0.10. 0.20 at temperatures 1.5 K≤T≤50 K and magnetic fields up to 15T. Their Van Vleck type magnetic susceptibility χ(T, B, x) strongly depends on the field atB≥6 T. The temperatureT _max(B, x) of the maximum of χ(T, B, x) decreases at increasing the field from zero to 15 T by approximately one order of magnitude for all Pr_1−x Y _x Ni₅ compounds. Changing the dilutionx from zero to 0.20, the field whereT _max(B, x) strongly drops is increased from 9 T to 11 T. Our data agree qualitatively with the predictions of a point charge model which considers the Zeeman term in addition to the electronic exchange and the dominating crystal field contributions.     

Densification involved in the UV-based photosensitivity of silicaglasses and optical fibers

A comprehensive survey of photosensitivity in silica glasses and optical fiber is reviewed. Recent work on understanding the mechanisms contributing to germanium or aluminum doped fiber photosensitivity is discussed within the framework of photoelastic densification models     

A new lateral MOS-gated thyristor with controlling base-current

A new lateral MOS-gated thyristor, called the Base-Current-Controlled Thyristor, is described. This device is designed so that most holes at the on-stage reach the P base through the floating P⁺ region adjacent to the P base and the on-state MOSFET. At the turn-off stage, the interruption of the hole current to the P base due to switching off the above MOSFET occurs simultaneously with the conventional turn-off operation. The concept of this device is verified experimentally by using the fabricated lateral device with the external MOSFET. This device exhibits a better trade-off relation between the on-state voltage and the turn-off time compared uith the conventional MOS-gated thyristor     

Series equivalence/operation of current-controlled boost-typesingle-phase voltage source converters for bidirectional power flow

Single-phase voltage source power converters (VSCs) under consideration are AC-DC current-controlled boost-type power converters with bidirectional power-handling capability. Equivalence between two series-connected two-level power converters and a single three-level power converter is considered here. Further considered is the series operation of three-level power converters. Simulation results and experimental verification for both are provided. Economical configurations of three-level power converters leading to multilevel waveforms are presented thereafter     

A wafer level monitoring method for plasma-charging damage usingantenna PMOSFET test structure

A novel monitoring method for plasma-charging damage is proposed. This method performs a quick and accurate evaluation using antenna PMOSFET. It was found that not only hot-carrier (HC) lifetime but transistor parameters such as initial gate current and substrate current were changed according to the degree of plasma-charging damage. However, the present work suggests that monitoring the shift of drain current after a few seconds of HC stress is a more accurate method to indicate plasma-charging damage. The monitoring method using the present test structure is demonstrated to be useful for realizing highly reliable devices     

Modulation and Equalisation Considerations for High Performance Radio LANs

The European Telecommunications Standards Institute (ETSI) has recently defined a European standard for a high performance radio LAN (known as HIPERLAN). To operate as wired LAN replacements, these systems will operate at 5.2 GHz and support instantaneous bit rates of just under 24 Mb/s. To counteract the time dispersive nature of the indoor radio channel, the use of adaptive equalisation is suggested. In this paper a number of possible modulation and equalisation techniques are presented and, in particular, the Bit Error Rate (BER) performance of quasi-coherent GMSK combined with Decision Feedback Equalisation is explored through computer simulation. The trade off between symbol spaced and fractionally spaced equalisation is considered together with the importance of feedfoward and feedback synchronisation to the channel's power delay profile. The paper also includes a comparison of the RLS and LMS based training algorithms and compares the modem developed under the ESPRIT III LAURA project with that specified in HIPERLAN.The application of dual antenna diversity is investigated and its impact on the number of received error free data packets obtained as a function of signal leval and rms delay spread. The use of such diversity is shown to greatly improve the BER performance of a HIPERLAN modem. The problem of frequency offset is considered and modifications are proposed to the HIPERLAN frame structure to improve the receiver's tolerance to such errors. Important practical issues such as frame and symbol synchronisation, frequency offset correction and hardware implementation are discussed from both the LAURA and HIPERLAN viewpoint.