Reactive Sintering of Copper Nanoparticles Using Intense Pulsed Light for Printed Electronics

Most commercial copper nanoparticles are covered with an oxide shell and cannot be sintered into conducting lines/films by conventional thermal sintering. To address this issue, past efforts have utilized complex reduction schemes and sophisticated chambers to prevent oxidation, thereby rendering the process cost ineffective. To alleviate these problems, we demonstrate a reactive sintering process using intense pulsed light (IPL) in the present study. The IPL process successfully removed the oxide shells of copper nanoparticles, leaving a conductive, pure copper film in a short period of time (2 ms) under ambient conditions. The in situ copper oxide reduction mechanism was studied using several different experiments and analyses. We observed instant copper oxide reduction and sintering through poly(N-vinylpyrrolidone) functionalization of copper nanoparticles, followed by IPL irradiation. This phenomenon may be explained by oxide reduction either via an intermediate acid created by ultraviolet (UV) light irradiation or by hydroxyl (-OH) end groups, which act like long-chain alcohol reductants.     

Thermoelectric Performance of Poly(3,4-Ethylenedioxy-thiophene)/Poly(Styrenesulfonate) Pellets and Films

The thermoelectric performance of poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonate) (PEDOT/PSS) pellets and free-standing PEDOT/PSS films, prepared from PEDOT/PSS solution containing the additives dimethyl sulfoxide or ethylene glycol, have been systematically investigated. It has been found that the electrical conductivity of free-standing PEDOT/PSS films is invariably much higher than that of PEDOT/PSS pellets, while there is no distinct change in the Seebeck coefficient. The highest electrical conductivity of a free-standing PEDOT/PSS film can be up to 300 S cm⁻¹, five to six times higher than that of PEDOT/PSS pellets (55 S cm⁻¹). The thermal conductivity was measured over a wide temperature range, indicating that PEDOT/PSS has extremely low thermal conductivity. The figure of merit (ZT) of free-standing PEDOT/PSS films with good environmental stability can be up to 10⁻², an order of magnitude higher than that of pressed PEDOT/PSS pellets (10⁻³).     

Interpretation of Absolute Laser Reflectance During Optical Monitoring of Polycrystalline GaAs Deposition on Quartz Using Metalorganic Chemical Vapor Deposition

Gallium arsenide (GaAs) was deposited by metalorganic chemical vapor deposition in a horizontal quartz reactor tube using trimethylgallium and arsine at 400°C to 500°C. Nucleation time and deposition rate were monitored using in situ laser reflectometry. This allowed differentiation between film and parasitic growth, which was not possible with other optical techniques. An absolute reflectance model was developed using measurements prior to GaAs deposition, and then employed to calculate values for GaAs on quartz. Detected reflectance intensities during experimental GaAs deposition were low compared with the model due to three-dimensional island growth, causing scattering of the incident laser radiation.     

Thin-Film Thermoelectric Module for Power Generator Applications Using a Screen-Printing Method

A new process for fabricating a low-cost thermoelectric module using a screen-printing method has been developed. Thermoelectric properties of screen-printed ZnSb films were investigated in an effort to develop a thermoelectric module with low cost per watt. The screen-printed Zn _x Sb_1−x films showed a low carrier concentration and high Seebeck coefficient when x was in the range of 0.5 to 0.57 and the annealing temperature was kept below 550°C. When the annealing temperature was higher than 550°C, the carrier concentration of the Zn _x Sb_1−x films reached that of a metal, leading to a decrease of the Seebeck coefficient. In the present experiment, the optimized carrier concentration of screen-printed ZnSb was 7 × 10¹⁸/cm³. The output voltage and power density of the ZnSb film were 10 mV and 0.17 mW/cm², respectively, at ΔT = 50 K. A thermoelectric module was produced using the proposed screen-printing approach with ZnSb and CoSb₃ as p-type and n-type thermoelectric materials, respectively, and copper as the pad metal.     

Effects of Double Substitution with Ge and Te on Thermoelectric Properties of a Skutterudite Compound

Studies have shown that the thermoelectric properties of CoSb₃ could be improved by the substitution of group IVB or VIB elements for Sb. However, the substitution volume is limited. To get a better picture of the substitution volume in view of thermoelectric properties, Ge and Te double-substituted skutterudite materials were prepared with the nominal composition of Co₄Sb _x Ge_5.9−0.5x Te_6.1−0.5x (x = 11, 10, 9, 8) by the traditional solid-state reaction method and spark plasma sintering, and Rietveld analysis was employed to refine the crystal structure. The results showed that the lattice parameter decreased linearly and the solubility limitations of group IVB and VIB elements were greatly alleviated by the Ge and Te codoping. Besides, the thermoelectric properties were analyzed through measurements of electrical and thermal conductivities as well as room-temperature electrical transport properties. The results showed that the substitution volume of Ge and Te could play an important role in the thermoelectric properties, and a minimum lattice thermal conductivity value of 1.56 W m⁻¹ K⁻¹ was obtained at around 673 K for Co₄Sb₈Ge_1.9Te_2.1. Co₄Sb₁₁Ge_0.4Te_0.6 achieved the best figure of merit of 0.89 at around 773 K, which was remarkably improved over that of untreated CoSb₃.     

Effects of Ce Addition on the Microstructure and Mechanical Properties of Sn-58Bi Solder Joints

The effects of a rare-earth element on the microstructure, mechanical properties, and whisker growth of Sn-58Bi alloys and solder joints in ball grid array (BGA) packages with Ag/Cu pads have been investigated. Mechanical testing indicated that the elongation of Sn-58Bi alloys doped with Ce increased significantly, and the tensile strength decreased slightly, in compar- ison with undoped Sn-58Bi. In addition, the growth of both fiber- and hillock-shaped tin whiskers on the surface of Sn-58Bi-0.5Ce was retarded in the case of Sn-3Ag-0.5Cu-0.5Ce alloys. The growth of interfacial intermetallic compounds (IMC) in Sn-58Bi-0.5Ce solder joints was slower than that in Sn-58Bi because the activity of Ce atoms at the interface of the Cu₆Sn₅ IMC/solder was reduced. The reflowed Sn-58Bi and Sn-58Bi-0.5Ce BGA packages with Ag/Cu pads had a ball shear strength of 7.91 N and 7.64 N, which decreased to about 7.13 N and 6.87 N after aging at 100°C for 1000 h, respectively. The reflowed and aged solder joints fractured across the solder balls with ductile characteristics after ball shear tests.     

A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.     

A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of \(-\,2\). Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is + 2/? 1 LSB and the INL is + 1.8/? 1.4 LSB, respectively. Under an 8-bit resolution and a 62.5 Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is \(1.6\,\upmu\)A under a 2.5 V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of \(400 \times 500\,{\mathrm{mm}}^2\).     

Nth order current mode universal filter using MOCCCIIs

This article presents a new current mode single-input-multiple-output nth order universal filter. The proposed circuit employs (n + 1) number multiple output second generation current conveyors and n number grounded capacitors only. Presented circuits can realize current mode low pass, high pass, band pass, notch and all pass responses simultaneously at different high output impedance terminals. The current mode filter circuit provides low input impedance by selecting the proper value of bias current and also has high output impedance, which is suitable for cascading. The circuit offers some important features such as resistor less realization, no passive component matching constraints, low sensitivity, electronic tunability and active-C realization. The functionality of the proposed filter circuit is tested with the PSPICE simulation, which is found to agree well with the proposed theory.     

A Cross-Layer Multi-Hop Simulator for IEEE 802.11e

In this work we simulate the ad hoc mode of IEEE 802.11e for routing optimisation. We simulate the behaviour of routing algorithms at the network layer by using a custom-made cross-layer network simulator developed by our team, which simultaneously considers the physical and Medium Access Control (MAC) layers. Although the simulator also supports the infrastructure mode, in this paper we focus on the ad hoc feature which was introduced by the authors. We opted for the simulator approach over the theoretical analysis, but we also present a mathematical model for IEEE 802.11 ad hoc networks. Some initial tests were performed by using a simple routing algorithm (to evaluate the behaviour of the system in terms of selection of the path between a source and a destination, and the correctness of the calculated metrics, which include end-to-end delay, packets lost, packets delivered), but more advanced cross-layer design solutions were also tested. When information from the physical and MAC layers is used as an input to the routing algorithm, improvements are achieved in the performance of the network. Several functions were compared and the algorithm that privileges shorter links accounting with the metric “collision rate” achieves the best results. When compared with a standard routing solution, this cross-layer approach allows to increase the number of packets delivered, while not significantly affecting the end-to-end delay of the packets.