Alternative Tilings for Improved Surface Area Estimates by Local Counting Algorithms

In this paper, we first review local counting methods for perimeter estimation of piecewise smooth binary figures on square, hexagonal, and triangular grids. We verify that better perimeter estimates, using local counting algorithms, can be obtained using hexagonal or triangular grids. We then compare surface area estimates using local counting techniques for binary three-dimensional volumes under the three semi-regular polyhedral tilings: the cubic, truncated octahedral, and rhombic dodecahedral tilings. It is shown that for surfaces of random orientation with a uniform distribution, the expected error of surface area estimates is smaller for the truncated octahedral and rhombic dodecahedral tilings than for the standard cubic or rectangular prism tilings of space. Additional properties of these tessellations are reviewed and potential applications of better surface area estimates are discussed.     

A field-portable thermal infrared grating spectrometer (THIRSPEC)

A thermal infrared grating spectrometer was developed for field studies in the Earth sciences. The design is based on a reflection grating and a 60-element HgCdTe detector array. The useful spectral range of the instrument covers 7.9-11.3 μm with a Nyquist limited resolution of 0.16 μm. The instrument averages over a 12° field of view and compares the exitance of the target to that of an internal black body at ambient temperature. The noise equivalent temperature is approximately 0.06°K over the useful spectral range. Background radiance reflected from the surface of the target can seriously impede the determination of emissivity. This effect is removed from the spectra of geological samples by the use of reference samples     

An investigation of the performance portability of OpenCL

This paper reports on the development of an MPI/OpenCL implementation of LU, an application-level benchmark from the NAS Parallel Benchmark Suite. An account of the design decisions addressed during the development of this code is presented, demonstrating the importance of memory arrangement and work-item/work-group distribution strategies when applications are deployed on different device types. The resulting platform-agnostic, single source application is benchmarked on a number of different architectures, and is shown to be 1.3–1.5× slower than native FORTRAN 77 or CUDA implementations on a single node and 1.3–3.1× slower on multiple nodes. We also explore the potential performance gains of OpenCL’s device fissioning capability, demonstrating up to a 3× speed-up over our original OpenCL implementation.     

Spatial Wavefunction-Switched (SWS) InGaAs FETs with II–VI Gate Insulators

This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (V _g). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance–voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance–voltage (C–V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described.     

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeO _x )-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Operation of integrated InGaAsP-InP optical amplifier-monitoringdetector with feedback control circuit

Monolithic integration of a monitoring detector with an optical amplifier simplifies the use of an amplifier in lightwave systems. The structure and performance are described of a monolithically integrated semiconductor optical amplifier with low-loss Y-branching waveguides and a monitoring p-i-n detector. The photocurrent of the integrated detector can be used as a single control parameter for amplifier output leveling, gain optimization, and in situ monitoring of facet antireflective coatings     

Scalable VLSI implementations for neural networks

This paper discusses research on scalable VLSI implementations of feed-forward and recurrent neural networks. These two families of networks are useful in a wide variety of important applications—classification tasks for feed-forward nets and optimization problems for recurrent nets—but their differences affect the way they should be built. We find that analog computation with digitally programmable weights works best for feed-forward networks, while stochastic processing takes advantage of the integrative nature of recurrent networks. We have shown early prototypes of these networks which compute at rates of 1–2 billion connections per second. These general-purpose neural building blocks can be coupled with an overall data transmission framework that is electronically reconfigured in a local manner to produce arbitrarily large, fault-tolerant networks.     

The isolation and nucleation of misfit dislocations in strained epitaxial layers grown on patterned,ion-damaged GaAs

As shown previously, the misfit dislocation density of strained epitaxial III–V layers can be significantly reduced by isolating sections (via patterned etching) of a GaAs substrate before epitaxial growth. A disadvantage of this technique is that the wafer surface is no longer planar, which can complicate subsequent device fabrication. As an alternative, we have investigated growth of 350 nm of In_0.5Ga{0.95}As by molecular beam epitaxy at two temperatures on substrates which were patterned and selectively damaged by Xe ion implantation (300 keV, 10¹⁵ cm²). Selectively etched substrates were prepared as reference samples as well. The propagation of the misfit dislocations was stopped by the ion-implanted regions of the low growth temperature (400° C) material, but the damaged portions also acted as copious nucleation sources. The resulting dislocation structure was highly anisotropic, with dislocation lines occurring in virtually only one direction. At the higher growth temperature (500° C) the defect density fell, but the ion damaged sections no longer blocked dislocation glide. Images from cathodoluminescence and transmission electron microscopy show thatthe low growth temperature material has a dislocation density of 70,000 cm^-1 in the 110 direction and less than 10,000 cm^-1 in the 110 direction. Ion channeling and x-ray diffraction show that strain is relieved in only one direction. The strain relief is consistent with the relief derived from TEM dislocation counts and Burgers vector determination. However, even this high dislocation count is not sufficient to reach the expected equilibrium strain. Reasons for the anisotropy are discussed.