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91.
In passive optical networks (PONs), the low effectiveness in terms of service utilization and network evolution have been important design issues. In this article, we introduce a hybrid access network architecture, so called scalable WDM-based Ethernet hybrid-PON (SWE-PON), which features a wavelength-division-multiplexed (WDM) feeder network using a combination of tunable laser device (TLD) and cyclic arrayed waveguide grating (AWG) and time-division-multiplexed (TDM) distribution network based on a reflective transmission mode. Necessary conditions needed to guarantee flawless packet transmission through normal WDM/TDM hierarchical PONs including the SWE-PON, are analyzed. We also propose a hierarchical fair time-window allocation mechanism which coordinates wavelength assignment and time-window bandwidth allocation so that high link utilization and fair bandwidth allocation are guaranteed in every multiplexing level.
Minho KangEmail:
  相似文献   
92.
A new fabrication method of a microlens is proposed that can be easily applied to optical devices and microlens systems. The proposed microlens is formed by self-surface tension and cohesion of UV curing material. Since the microlens is hardened by short time UV exposure, the fabrication process is very simple. Integration with surface emitting-light emitting diode (SE-LED) results in enhanced coupling to optical fiber with coupling efficiency larger than the conventional case by 1.5 times. We also made a hemispheric microlensed fiber using this method. Compared with a typical arc-lensed fiber and a flat-end fiber, the coupling efficiency is improved to 18% and 40%, respectively  相似文献   
93.
A power-factor controller for single-phase PWM rectifiers   总被引:1,自引:0,他引:1  
A novel power-factor controller for single-phase pulsewidth modulated rectifiers is proposed. The unity power-factor controller for a sinusoidal input current is derived using the feedback linearization concept. Two active switches and two diodes are utilized for AC-to-DC power conversion. Experimental results obtained on a 4 kW prototype are discussed  相似文献   
94.
95.
3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.  相似文献   
96.
The fluctuation of available link bandwidth in mobilecellular networks motivates the study of adaptive multimediaservices, where the bandwidth of an ongoing multimedia call can bedynamically adjusted. We analyze the diverse objectives of theadaptive multimedia framework and propose two bandwidth adaptationalgorithms (BAAs) that can satisfy these objectives. The firstalgorithm, BAA-RA, takes into consideration revenue and``anti-adaptation' where anti-adaptation means that a user feelsuncomfortable whenever the bandwidth of the user's call ischanged. This algorithm achieves near-optimal total revenue withmuch less complexity compared to an optimal BAA. The secondalgorithm, BAA-RF, considers revenue and fairness, and aims at themaximum revenue generation while satisfying the fairnessconstraint defined herein. Comprehensive simulation experimentsshow that the difference of the total revenue of BAA-RA and thatof an optimal BAA is negligible. Also, numerical results revealthat there is a conflicting relationship between anti-adaptationand fairness.  相似文献   
97.
We demonstrate an all-monolithic metal-organic chemical vapor epitaxy (MOCVD)-grown 1.55-/spl mu/m vertical-cavity surface-emitting laser operating continuous wave up to 35/spl deg/C. The structure is based on the InAlGaAs-InP material system grown by a single step of MOCVD. Wet oxidation of a strained In/sub 0.4/Al/sub 0.6/As layer is used for the current confinement. The threshold current, threshold voltage and the external quantum efficiency at room temperature are about 1.6 mA, 2.3 V, and 5.4%, respectively.  相似文献   
98.
A new physics-based noise model of a GaAs PHEMT is developed using the characteristic potential method (CPM). The model calculates the intrinsic noise current sources using CPM. Combined with the extrinsic noise parameters extracted from the measured S-parameters, the model reproduces four noise parameters of the device accurately under low drain bias voltages without using any fitting parameters. The model is verified with a 0.2-/spl mu/m GaAs PHEMT and shows excellent agreement with the measurements for all the noise parameters up to a drain voltage of 1 V Also, the proposed method allows the simulation of the microscopic noise distribution and thus allows one to obtain a physical understanding of noise mechanisms inside the device.  相似文献   
99.
A simple and accurate parameter-extraction method of a high-frequency small-signal MOSFET model including the substrate-related parameters and nonreciprocal capacitors is proposed. Direct extraction of each parameter using a linear regression approach is performed by Y-parameter analysis on the proposed equivalent circuit of the MOSFET for high-frequency operation. The extracted results are physically meaningful and good agreement has been obtained between the simulation results of the equivalent circuit and measured data without any optimization. Also, the extracted parameters, such as gm and gds, match very well with those obtained by DC measurement  相似文献   
100.
We present a novel operational amplifier preset technique for a switched‐capacitor circuit to reduce the acquisition time by improving the slewing. The acquisition time of a variable gain amplifier (VGA) using the proposed technique is reduced by 30% compared with a conventional one; therefore, the power consumption of the VGA is decreased. For additional power reduction, a programmable capacitor array scheme is used in the VGA. In the 0.13 μm CMOS process, the VGA, which consists of three‐stages, occupies 0.33 mm2 and dissipates 19.2 mW at 60 MHz with a supply voltage of 1.2 V. The gain range is 36.03 dB, which is controlled by a 10‐bit control word with a gain error of ±0.68 LSB.  相似文献   
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