Interfacial reaction between 42Sn-58Bi solder and electroless Ni-P/immersion Au under bump metallurgy during aging

The interfacial reaction between 42Sn-58Bi solder (in wt.% unless specified otherwise) and electroless Ni-P/immersion Au was investigated before and after thermal aging, with a focus on the formation and growth of an intermetallic compound layer, consumption of under bump metallurgy (UBM), and bump shear strength. The immersion Au layer with thicknesses of 0 μm (bare Ni), 0.1 μm, and 1 μm was plated on a 5-μm-thick layer of electroless Ni-P (with 14–15 at.% P). The 42Sn-58Bi solder balls were then fabricated on three different UBM structures by using screen printing and pre-reflow. A Ni₃Sn₄ layer formed at the joint interface after the pre-reflow for all three UBM structures. On aging at 125°C, a quaternary phase, identified as Sn₇₇Ni₁₅Bi₆Au₂, was observed above the Ni₃Sn₄ layer in the UBM structures that contain Au. The thick Sn₇₇Ni₁₅Bi₆Au₂ layer degraded the integrity of the solder joint, and the shear strength of the solder bump was about 40% less than the nonaged joints.     

Parallel in-core and out-of-core solution of electrically large problems using the RWG basis functions

Currently, the problem size that can be solved in reasonable time using the Method of Moments is limited by the amount of memory installed in the computer. This paper offers a new development that not only breaks this memory constraint, but also maintains the efficiency of running the problem in-core. In this paper, highly efficient parallel matrix-filling schemes are presented for parallel in-core and parallel out-of-core integral-equation solvers with subdomain RWG basis functions. The parallel methodology for matrix filling is quite different when using a subdomain basis as opposed to using a higher-order basis. The parallel in-core solver uses memory, which is often expensive and limited in size. The parallel out-of-core solver is introduced to extend the capability of MoM to solve larger problems that can be as large as the amount of storage on the hard disk. Numerical results on several typical computer platforms show that the parallel matrix-filling schemes and matrix-equation solvers introduced here are highly efficient and achieve theoretical predictions. The implementation of these advancements with the widely used RWG basis functions creates a powerful tool for efficient computational electromagnetics solution of complex real-world problems.     

A Skin‐Inspired Substrate with Spaghetti‐Like Multi‐Nanofiber Network of Stiff and Elastic Components for Stretchable Electronics

Mimicking the skin's non‐linear self‐limiting mechanical characteristics is of great interest. Skin is soft at low strain but becomes stiff at high strain and thereby can protect human tissues and organs from high mechanical loads. Herein, the design of a skin‐inspired substrate is reported based on a spaghetti‐like multi‐nanofiber network (SMNN) of elastic polyurethane (PU) nanofibers (NFs) sandwiched between stiff poly(vinyldenefluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) NFs layers embedded in polydimethylsiloxane elastomer. The elastic moduli of the stretchable skin‐inspired substrate can be tuned in a range that matches well with the mechanical properties of skins by adjusting the loading ratios of the two NFs. Confocal imaging under stretching indicates that PU NFs help maintain the stretchability while adding stiff P(VDF‐TrFE) NFs to control the self‐limiting characteristics. Interestingly, the Au layer on the substrate indicates a negligible change in the resistance under cyclic (up to 7000 cycles at 35% strain) and dynamic stretching (up to 35% strain), which indicates the effective absorption of stress by the SMNN. A stretchable chemoresistive gas sensor on the skin‐inspired substrate also demonstrates a reasonable stability in NO₂ sensing response under strain up to 30%. The skin‐inspired substrate with SMNN provides a step toward ultrathin stretchable electronics.     

Quasi-cyclic dyadic codes in the Walsh-Hadamard transform domain

A code is s-quasi-cyclic (s-QC) if there is an integer s such that cyclic shift of a codeword by s-positions is also a codeword. For s = 1, cyclic codes are obtained. A dyadic code is a code which is closed under all dyadic shifts. An s-QC dyadic (s-QCD) code is one which is both s-QC and dyadic. QCD codes with s = 1 give codes that are cyclic and dyadic (CD). We obtain a simple characterization of all QCD codes (hence of CD codes) over any field of odd characteristic using Walsh-Hadamard transform defined over that finite field. Also, it is shown that dual a code of an s-QCD code is also an s-QCD code and s-QCD codes for a given dimension are enumerated for all possible values of s.     

A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique

A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25-MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35-/spl mu/m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48-dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC's minimum operating power supply is 1.3 V (|V/sub TH,P/| = 0.9 V) and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes.     

Capacity improvement in CDMA downlink with orthogonal code-hopping multiplexing

Orthogonal code-hopping multiplexing (OCHM) is a statistical multiplexing scheme designed to increase the number of allowable downlink channels in code division multiple access (CDMA) systems. OCHM is expected to compensate for a lack of codewords in future communication systems. In CDMA systems including OCHM, system capacity is limited by the number of codewords and power (or interference), and the maximum system capacity is determined by a stronger limitation between them. Call blockings due to power limitation may occur firstly if downlink channels demand large E/sub b//I/sub 0/ values and a high-channel activity. On the other hand, code limitation may occur prior to power limitation in CDMA. The maximum system capacities determined by both code and power limitations must be known, even in OCHM. However, previous studies on OCHM system capacity focused only on increasing the number of multiplexed users with no consideration of the power limitation. In this paper, the overall system capacity of OCHM considering both code and power limitations was evaluated. For this analysis, the transmission chip energy of base station (BS) and inner/outer-cell interference is mathematically derived in a multicell and multiuser environment. The downlink system capacity for OCHM is larger than for orthogonal code division multiplexing (OCDM) as other cell interference (OCI), mean channel activity, and the required E/sub b//I/sub 0/ value decrease.     

Modeling growth rate of HfO2 thin films grown by metal-organic molecular beam epitaxy

HfO₂ dielectric layers were grown on the p-type Si (100) substrate by metal-organic molecular beam epitaxy (MOMBE). Hafnium-tetra-butoxide, Hf(O·t-C₄H₉)₄ was used as a Hf precursor and Argon gas was used as a carrier gas. The thickness of the HfO₂ film and intermediate SiO₂ layer were measured by scanning electron microscopy (SEM) and high-resolution transmission electron microscopy (HRTEM). The properties of the HfO₂ layers were evaluated by X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), high frequency (HF) capacitance-voltage (C-V) measurement, and current-voltage (I-V) measurement. C-V and I-V measurements have shown that HfO₂ layer grown by MOMBE has a high dielectric constant (k) of 20-22 and a low-level of leakage current density. The growth rate is affected by various process variables such as substrate temperature, bubbler temperature, Ar and O₂ gas flows and growth time. Since the ratio of O₂ and Ar gas flows are closely correlated, the effect of variations in O₂/Ar flow ratio on growth rate is also investigated using statistical modeling methodology.     

Universal Filtering Via Hidden Markov Modeling

The problem of discrete universal filtering, in which the components of a discrete signal emitted by an unknown source and corrupted by a known discrete memoryless channel (DMC) are to be causally estimated, is considered. A family of filters are derived, and are shown to be universally asymptotically optimal in the sense of achieving the optimum filtering performance when the clean signal is stationary, ergodic, and satisfies an additional mild positivity condition. Our schemes are comprised of approximating the noisy signal using a hidden Markov process (HMP) via maximum-likelihood (ML) estimation, followed by the use of the forward recursions for HMP state estimation. It is shown that as the data length increases, and as the number of states in the HMP approximation increases, our family of filters attains the performance of the optimal distribution-dependent filter. An extension to the case of channels with memory is also established.     

A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.