Computational study of band-crossing reactions

A numerical study of band-crossing reactions is conducted using a quasi-one-dimensional (1-D) computational model that accounts for species bulk advection, electromigration velocities, diffusion, and chemical reaction. The model is used to simulate chemical reactions between two initially distinct sample zones, referred to as "bands," that cross each other due to differences in electromigration velocities. The reaction is described in terms of a single step, reversible mechanism involving two reactants and one product. A parametric study is first conducted of the behavior of the species profiles, and results are interpreted in terms of the Damko/spl uml/hler number and of the ratios of the electromigration velocities of the reactant and product. Computed results are then used to explore the possibility of extracting forward and backward reaction rates based on time resolved observation of integral moments of species concentrations. In particular, it is shown that in the case of fast reactions, robust estimates can be obtained for high forward rates, but that small reverse rates may not be accurately observed.     

Effect of Fe2O3 as an Aggregate Replacement on Mechanical,and Gamma/ Neutron Radiation Shielding Properties of Phosphoaluminate Glasses

Journal of Inorganic and Organometallic Polymers and Materials - In the present work, we examined the impact of Fe2O3 on the mechanical and photon shielding characteristics of lead-phosphoaluminate...     

Power estimation techniques for FPGAs

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.     

A technique for Improving dual-output domino logic

We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24%, respectively, over dual-output domino and a 48% power reduction for the largest circuit.     

Design and implementation of a high level programming environmentfor FPGA-based image processing

Reconfigurable hardware in the form of field programmable gate arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution. However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, the authors present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Their approach is to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations