Quantification of surface damage of tool steels after EDM

The surface transformation and damage in AISI O1, A2, D2 and D6 tool steels after EDM were investigated. The results show that the recast layer is composed of two distinct layers: a topmost layer solidifying inwards from the specimen surface and an intermediate layer solidifying outwards from the base of the molten metal. The depth of surface cracks is found to correlate well with the thickness of the white layer, the latter being a layer of rapidly solidified material which, depending on the tool steel material, may consist either primarily of the topmost recast layer, or both the topmost and a large part of the intermediate recast layer. The density of surface cracks, however, correlates better with the thickness of the overall recast layer.

Attempts were made to quantify the depth of white (or damaged) layer with respect to the process parameters and surface roughness after EDM. It is found that with a fixed dielectric and flushing condition, the damaged layer correlates well with the pulse energy irrespective of thetool steel material. On the other hand, even though the thickness of the white layer increases with the surface roughness, the result shows considerably more scatter. Based on the present findings, ways of estimating the depth of the damaged layer produced by EDM are proposed.     

Novel Collision Detection and Avoidance System for Midvehicle Using Offset-Based Curvilinear Motion

In recent days, the manufacture of automotive vehicles is dramatically enhanced worldwide. Most vehicle crashes are due to the drive distraction on the real highway roads and traffic-density. In this proposed method, a novel collision detection and avoidance algorithm are coined for Midvehicle Collision Detection and Avoidance System (MCDAS), addressing two scenarios, namely, (a) A rear-end collision avoidance with host vehicle under no front-end vehicle condition and (b) offset-based curvilinear motion under critical conditions, while, suitable parallel parking manoeuvring also addressed using offset-based curvilinear motion. The Monte Carlo analysis of the proposed MCDAS is demonstrated using the Constant Velocity (CV) manoeuvring strategy and simulated with real-time data using the NGSIM database.

     

In Situ Liquid-Cell TEM Observation of Multiphase Classical and Nonclassical Nucleation of Calcium Oxalate

Calcium oxalate (CaOx) is the major phase in kidney stones and the primary calcium storage medium in plants. CaOx can form crystals with different lattice types, water contents, and crystal structures. However, the conditions and mechanisms leading to nucleation of particular CaOx crystals are unclear. Here, liquid-cell transmission electron microscopy and atomistic molecular dynamics simulations are used to study in situ CaOx nucleation at different conditions. The observations reveal that rhombohedral CaOx monohydrate (COM) can nucleate via a classical pathway, while square COM can nucleate via a non-classical multiphase pathway. Citrate, a kidney stone inhibitor, increases the solubility of calcium by forming calcium-citrate complexes and blocks oxalate ions from approaching calcium. The presence of multiple hydrated ionic species draws additional water molecules into nucleating CaOx dihydrate crystals. These findings reveal that by controlling the nucleation pathways one can determine the macroscale crystal structure, hydration state, and morphology of CaOx.     

A Single-Phase Boost Rectifier System for Wide Range of Load Variations

Converters operated in discontinuous-conduction-mode (DCM) and in continuous-conduction-mode (CCM) are suitable for lighter and higher loads, respectively. A new, constant switching frequency based single-phase rectifier system is proposed, which operates in DCM and in CCM for outputs less than and greater than 50% rated load, respectively, covering a wide range of load variation. The power circuit and the control circuit of the proposed rectifier are easily configurable for DCM and CCM operations. The measured load current is used to select the desired operating mode. The peak device current under DCM is limited to rated device current under CCM without using a device of higher current rating. The input current shaping under CCM and DCM are based on the comparison of measured input current with linear and nonlinear carriers, respectively. A load current feedforward scheme is presented to improve the system dynamic performance and also to ensure a smooth transition between the two operating modes. All the necessary control operations are performed without using multiplication, division and square-root operation. The proposed rectifier shows improved input current characteristics over the existing CCM converters for the above load range. This is validated on a 600-W rectifier prototype. Simulation and experimental results are presented     

Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits

Today’s analog/RF design and verification face significant challenges due to circuit complexity, process variations and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this paper, we propose a methodology for modeling and verification of analog/RF designs in the presence of noise and process variations. Our approach is based on modeling the designs using stochastic differential equations (SDE) that will allow us to incorporate the statistical nature of noise. We also integrate the device variation due to 0.18μ m fabrication process in an SDE based simulation framework for monitoring properties of interest in order to quickly detect errors. Our approach is illustrated on nonlinear Tunnel-Diode and a Colpitts oscillator circuits.     

Comparative study of drift region designs in RF LDMOSFETs

Systematic investigation of the drift region design of the RF LDMOSFET in terms of breakdown voltage, on-resistance, transconductance, capacitance and hot-carrier effects is presented. The incorporation of a source field plate allows for an increase of drift dose for a given breakdown voltage, which eases the tradeoff between the breakdown voltage and on-resistance, and the breakdown voltage and transconductance. However, the increased dose can significantly degrade hot-carrier reliability. A step-drift has enhanced hot-carrier immunity and lower capacitance, but, at the cost of increased on-state resistance and lower transconductance. Furthermore, a second origin of hot carriers is reported in the step-drift design, which may cause damage in the drift region. A deeper drift region design, which does not require an additional mask in comparison to the step-drift design, is investigated. The proposed approach shares all the advantages provided by the field plate design. Moreover, the lower concentration in the new drift region design leads to enhanced hot-carrier immunity.     

Design of serial concatenated MSK schemes based on density evolution

We consider the design of convolutional codes and low density parity check (LDPC) codes with minimum-shift keying (MSK) when the receiver employs iterative decoding and demodulation. The main idea proposed is the design of coded schemes that are well matched to the iterative decoding algorithm being used rather than to hypothetical maximum-likelihood decoding. We first show that the design is crucially dependent on whether the continuous phase encoder (CPE) is realized in recursive form or in nonrecursive form. We then consider the design of convolutionally coded systems and low density parity check codes with MSK to obtain near-capacity performance. With convolutional codes, we show that it is possible to improve the performance significantly by using a mixture of recursive and nonrecursive realizations for the CPE. For low density parity check codes, we show that codes designed for binary phase shift keying are optimal for MSK only if the nonrecursive realization is used; for the recursive realization, we design new LDPC codes based on the concept of density evolution. We show that these codes outperform the best known codes for MSK and have lower decoding complexity.     

Band-rejection fibre filter using periodic core deformation

Grating-based all-fibre bandstop filters were fabricated by introducing periodic deformations in the core of the fibre with a CO₂ laser by first ablating the surface of the fibre and then annealing it. These devices, which can be tailored to any wavelength, have a broad bandwidth (10 nm), high peak wavelength rejection (>20 dB), low insertion loss (<0.3 dB), a very flat response outside the rejection band, and a short physical length (6 mm)     

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K ×2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.     

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V _dd assignment, multiple V _th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.