Design of high-speed data transfer turbo code for body channel communication transceivers

In this work, a digital differential transmitter based on low-power wireless compensation transceiver for body channel communication (BCC) is proposed. Further, the proposed transceiver is composed of Touch Status Detection Unit (TSDU), Wireless Status Compensation Unit (WSCU), and a reconfigurable preamplifier. Initially, the human body channel environment for wireless communication is investigated based on properties from 1 to 100 MHz. Further, the turbo code-based encoding scheme is used to encode the data before transferring the data on the transmitter side. Also, the proposed error-correcting parallel turbo decoder using a modified step-by-step algorithm is presented. The turbo code-based decoding scheme is used to recover the error-free transmitted data at the receiver side. Results demonstrate that the proposed BCC transceiver is designed using 90 nm CMOS technology and it is observed that the proposed BCC transceiver has utilized an area of 600mm². Also, the maximum data rate achieved by a proposed BCC transceiver was 100 Mbps, and the overall transceiver power consumption is 0.42 mW, and energy for communication is 0.02 nj/b.     

Network Lifetime Enhancement of Wireless Sensor Networks Using EFRP Protocol

This paper presents a novel transceiver architecture for in-band full duplex radio. A transceiver for full duplex radio requires a self-interference (SI) canceler to remove the SI occurring from the transmitter to the receiver, and a full duplex transceiver generally has two SI cancelers: one at the analog RF stage and the other at the baseband stage. The output from the SI canceler at the RF stage includes much residual SI, and it decreases the number of bits allocated to the analog baseband signal at the analog-to-digital converter. A 1-tap analog baseband SI canceler that uses a replica signal including only the direct path component of the residual SI has been presented for preventing degradation. However, the architecture cannot remove the SI well due to the high Ricial K-factor. To address the problem, the presented architecture has an SI canceler at the analog baseband stage, and this canceler employs a replica signal that is output from a digital-to-analog converter. Because the replica signal is generated in the digital domain, the architecture can generate a multipath replica signal, and improved performance can be expected. Numerical and theoretical analyses are shown to validate the effectiveness of the presented architecture.

     

Stress Reduction of 3D Printed Compliance‐Tailored Multilayers

Multilayered multi‐material interfaces are encountered in an array of fields. Here, enhanced mechanical performance of such multi‐material interfaces is demonstrated, focusing on strength and stiffness, by employing bondlayers with spatially‐tuned elastic properties realized via 3D printing. Compliance of the bondlayer is varied along the bondlength with increased compliance at the ends to relieve stress concentrations. Experimental testing to failure of a tri‐layered assembly in a single‐lap joint configuration, including optical strain mapping, reveals that the stress and strain redistribution of the compliance‐tailored bondlayer increases strength by 100% and toughness by 60%, compared to a constant modulus bondlayer, while maintaining the stiffness of the joint with the homogeneous stiff bondlayer. Analyses show that the stress concentrations for both peel and shear stress in the bondlayer have a global minimum when the compliant bond at the lap end comprises ≈10% of the bondlength, and further that increased multilayer performance also holds for long (relative to critical shear transfer length) bondlengths. Damage and failure resistance of multi‐material interfaces can be improved substantially via the compliance‐tailoring demonstrated here, with immediate relevance in additive manufacturing joining applications, and shows promise for generalized joining applications including adhesive bonding.     

Parameter-uniform hybrid numerical scheme for time-dependent convection-dominated initial-boundary-value problems

In this paper, we propose a numerical scheme which is almost second-order spatial accurate for a one-dimensional singularly perturbed parabolic convection-diffusion problem exhibiting a regular boundary layer. The proposed numerical scheme consists of classical backward-Euler method for the time discretization and a hybrid finite difference scheme for the spatial discretization. We analyze the scheme on a piecewise-uniform Shishkin mesh for the spatial discretization to establish uniform convergence with respect to the perturbation parameter. Numerical results are presented to validate the theoretical results.     

Automated dynamic detection of busy–wait synchronizations

With the advent of multicores, multithreaded programming has acquired increased importance. In order to obtain good performance, the synchronization constructs in multithreaded programs need to be carefully implemented. These implementations can be broadly classified into two categories: busy–wait and schedule‐based. For shared memory architectures, busy–wait synchronizations are preferred over schedule‐based synchronizations because they can achieve lower wakeup latency, especially when the expected wait time is much shorter than the scheduling time. While busy–wait synchronizations can improve the performance of multithreaded programs running on multicore machines, they create a challenge in program debugging, especially in detecting and identifying the causes of data races. Although significant research has been done on data race detection, prior works rely on one important assumption—the debuggers are aware of all the synchronization operations performed during a program run. This assumption is a significant limitation as multithreaded programs, including the popular SPLASH‐2 benchmark have busy–wait synchronizations such as barriers and flag synchronizations implemented in the user code. We show that the lack of knowledge of these synchronization operations leads to unnecessary reporting of numerous races. To tackle this problem, we propose a dynamic technique for identifying user‐defined synchronizations that are performed during a program run. Both software and hardware implementations are presented. Furthermore, our technique can be easily exploited by a record/replay system to significantly speedup the replay. It can also be leveraged by a transactional memory system to effectively resolve a livelock situation. Our evaluation confirms that our synchronization detector is highly accurate with no false negatives and very few false positives. We further observe that the knowledge of synchronization operations results in 23% reduction in replay time. Finally, we show that using synchronization knowledge livelocks can be efficiently avoided during runtime monitoring of programs. Copyright © 2009 John Wiley & Sons, Ltd.     

Richardson extrapolation technique for singularly perturbed parabolic convection–diffusion problems

This paper deals with the study of a post-processing technique for one-dimensional singularly perturbed parabolic convection–diffusion problems exhibiting a regular boundary layer. For discretizing the time derivative, we use the classical backward-Euler method and for the spatial discretization the simple upwind scheme is used on a piecewise-uniform Shishkin mesh. We show that the use of Richardson extrapolation technique improves the ε-uniform accuracy of simple upwinding in the discrete supremum norm from O (N ⁻¹ ln N + Δt) to O (N ⁻² ln² N + Δt ²), where N is the number of mesh-intervals in the spatial direction and Δt is the step size in the temporal direction. The theoretical result is also verified computationally by applying the proposed technique on two test examples.     

A system for debugging via online tracing and dynamic slicing

Dynamic slicing is a promising trace based technique that helps programmers in the process of debugging. In order to debug a failed run, dynamic slicing requires the dynamic dependence graph (DDG) information for that particular run. The two major challenges involved in utilizing dynamic slicing as a debugging technique are the efficient computation of the DDG and the efficient computation of the dynamic slice, given the DDG. In this paper, we present an efficient debugger, which first computes the DDG efficiently while the program is executing; dynamic slicing is later performed efficiently on the computed DDG, on demand. To minimize program slowdown during the online computation of DDG, we make the design decision of not outputting the computed dependencies to a file, instead, storing them in memory in a specially allocated fixed size circular buffer. The size of the buffer limits the length of the execution history that can be stored. To maximize the execution history that can be maintained, we introduce optimizations to eliminate the storage of most of the generated dependencies, at the same time ensuring that those that are stored are sufficient to capture the bug. Experiments conducted on CPU‐intensive programs show that our optimizations are able to reduce the trace rate from 16 to 0.8 bytes per executed instruction. This enables us to store the dependence trace history for a window of 20 million executed instructions in a 16‐MB buffer. Our debugger is also very efficient, yielding slicing times of around a second, and only slowing down the execution of the program by a factor of 19 during the online tracing step. Using recently proposed architectural support for monitoring, we are also able to handle multithreaded programs running on multicore processors. Copyright © 2011 John Wiley & Sons, Ltd.     

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.