40-Gb/s circuits built from a 120-GHz f/sub T/ SiGe technology

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. In this paper we first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower BV/sub CEO/ and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4: 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a -3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220-/spl Omega/ gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over -100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the BV/sub CEO/ of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.     

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.     

A Two-dimensional Full-wave Finite-difference Frequency-domain Analysis of Ferrite Loaded Structures

A two-dimensional (2-D) full-wave finite-difference frequency-domain (FDFD) method is presented for analyzing the dispersion characteristics of transversely magnetized ferrite loaded structures. Results for a number of different ferrite loaded structures are presented. The accuracy of the FDFD formulation is verified by comparing the numerical results with analytical results and those obtained using the FDTD method, and very good agreement is obtained.     

Design and analysis of multifrequency Wilkinson power dividers using nonuniform transmission lines

In this article, based on nonuniform transmission lines, the design of compact multifrequency Wilkinson power dividers (WPDs) is presented. This is accomplished by replacing the quarter‐wave uniform transmission lines in the conventional WPD by multiband nonuniform transmission line transformers (NTLTs). The design of these NTLTs is performed under the even mode analysis of the WPD. A single isolation resistor is used between the two output ports whose value is determined using the simple odd mode analysis of the WPD. For verification purposes, a triple‐frequency WPD and a quad‐frequency WPD are designed, simulated, fabricated, and measured. The results of the full‐wave simulations and the measurements verify the validity of the design procedure. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

iHOME: Index-Based JOIN Query Optimization for Limited Big Data Storage

Query optimization in Big Data becomes a promising research direction due to the popularity of massive data analytical systems such as Hadoop system. The query optimization is getting hard to efficiently execute JOIN queries on top of Hadoop query language, Hive, over limited Big Data storages. According to our previous work, HiveQL Optimization for JOIN query over Multi-session Environment (HOME) system has been introduced over Hadoop system to improve its performance by storing the intermediate results to avoid repeated computations. Time overheads and Big Data storages limitation are considered the main drawback of the HOME system, especially in the case of using additional physical storages or renting extra virtualized storages. In this paper, an index-based system for reusing data called indexing HiveQL Optimization for JOIN over Multi-session Big Data Environment (iHOME) is proposed to overcome HOME overheads by storing only the indexes of the joined rows instead of storing the full intermediate results directly. Moreover, the proposed iHOME system addresses eight cases of JOIN queries which classified into three groups; Similar-to-iHOME, Compute-on-iHOME, and Filter-of-iHOME. According to the experimental results of the iHOME system using TPC-H benchmark, it is found that the execution time of eight JOIN queries using iHOME on Hive has been reduced. Also, the stored data size in the iHOME system is reduced relative to the HOME system, as well as, the Big Data storage is saved. So, by increasing stored data size, the iHOME system guarantees the space scalability and overcomes the storage limitation.     

CAD modeling of coplanar waveguide interdigital capacitor

A lumped‐element circuit is proposed to model a coplanar waveguide (CPW) interdigital capacitor (IDC). Closed‐form expressions suitable for CAD purposes are given for each element in the circuit. The obtained results for the series capacitance are in good agreement with those available in the literature. In addition, the scattering parameters obtained from the circuit model are compared with those obtained using the full‐wave method of moments (MoM) and good agreement is obtained. Moreover, a multilayer feed‐forward artificial neural network (ANN) is developed to model the capacitance of the CPW IDC. It is shown that the developed ANN has successfully learned the required task of evaluating the capacitance of the IDC. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005.     

Circular antenna array synthesis using firefly algorithm

In this article, the design of circular antenna arrays (CAAs) and concentric circular antenna arrays (CCAAs) of isotropic radiators with optimum side lobe level (SLL) reduction is studied. The newly proposed global evolutionary optimization method; namely, the firefly algorithm (FA) is used to determine an optimum set of weights and positions for CAAs, and an optimum set of weights for CCAAs, that provides a radiation pattern with optimum SLL reduction with the constraint of a fixed major lobe beamwidth. The FA represents a new algorithm for optimization problems in electromagnetics. It is shown that the FA results provide a SLL reduction that is better than that obtained using well‐known algorithms, like the particle swarm optimization, genetic algorithm (GA), and evolutionary programming. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:139–146, 2014.     

ICs for 100-Gb/s serial operation

Recently, research activities in the field of 100 Gb/s integrated circuits (ICs) for communication systems have increased. This article discusses an overview of the building blocks of a hypothetical 100-Gb/s serial transmission system and points out some important aspects of such building blocks. Several key building blocks for a 100-Gb/s serial transceivers are also demonstrated. Some pioneering 100-Gb/s ICs designed through various enabling semiconductor technologies are presented as well.     

InP DHBT technology and design methodology for high-bit-rateoptical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions