用电子束曝光方法在优化设计的绝缘体上硅脊状波导上实现布拉格光栅的制作和评价

报道了一种用电子束曝光的方法在绝缘体上硅的脊状光波导上制做布拉格光栅的技术.考虑到实际的光子学集成的应用,讨论了这个带有布拉格光栅的脊状光波导的优化设计,给出了该布拉格光栅的测试和理论模拟结果.通过薄化绝缘体上硅的波导层的厚度和光栅的深腐蚀加工,获得了高达30cm-1的光栅耦合系数.     

Advances in Digital Front-End and Software RF Processing:Part I

One of the biggest technology trends in wirelessbroadband, radar, sonar, and broadcasting systems issoftware radio frequency processing and digitalfront-end. This trend encompasses a broad range oftopics, from circuit design and signal processing to systemintegration. It includes digital up-conversion (DUC) and     

Two-tone metal pattern transfer technique using a single mold surface

There is growing demand for a fine metal-patterning technique to fabricate devices of the next generation, such as patterned media, plasmon photonics, and nanoscale electrodes. Nanotransfer printing (nTP) using a nanoscale patterned stamp has recently received considerable attention because of its high throughput and high resolution. To increase the throughput of the process further, it will be necessary to be able to use the stamp repeatedly, because fabrication of the stamp is a comparatively lengthy process. However, after the first transfer process, residual metal in the concave areas of the stamp obstructs the continuation of the transfer process. We examined a two-tone metal pattern transfer technique using a single mold after the first transfer process. The obstructive gold pattern in the mold could be removed and obtained as a negative tone by using a layer of polymer as a transfer substrate.     

Effects of PAI on interface properties between HfSiO gate dielectric and silicon substrate

The effects of preamorphization implantation (PAI) on the interface properties between hafnium-silicate (HfSiO) gate dielectrics and silicon substrates were examined. In the case of an NH/sub 3/ nitrided interface, it was found that the PAI can improve the interface trap density (D/sub IT/) compared with the no PAI case. However, for the PAI samples, it was also found that samples with sacrificial screening oxide (Sac Ox) had worse interface properties compared with the samples without Sac Ox. It is attributed to the recoiled oxygen from Sac Ox during PAI.     

Residual stress evaluation in resin-molded IC chips using finite element analysis and piezoresistive gauges

The high residual stress in a resin-molded electronic package sometimes makes the electronic functions unstable. Therefore the residual stress in electronic packages, especially on the top surfaces of semiconductor chips, should be evaluated. The objective of this study is to present a simple method for evaluating residual stress in resin-molded semiconductor chips using a combination of experimental and numerical methods. The actual residual stress of the packaging process was measured by using test chips that included piezoresistive gauges. A linear thermoelastic finite element analysis was then carried out using a three-dimensional model. The finite element analysis was performed under a stress-free temperature determined by the temperature dependence of the residual stress, which was experimentally measured by using the piezoresistive test chips. The measured residual stress using the test chips agreed well with the results of the finite element analysis. It was therefore confirmed that the present evaluation method, combining experimental and numerical methods, is reliable and reasonable.     

Experimental and numerical analysis of channel-length-dependent electrical properties in bottom-gate,bottom-contact organic thin-film transistors with Schottky contact

Channel length dependence of field-effect mobility and source/drain parasitic resistance in pentacene thin-film transistors with a bottom-gate, bottom-contact configuration was investigated. Schottky barrier effect such as nonlinear behaviors in transistor output characteristics appeared and became more prominent for shorter channel length less than 10 μm, raising some concerns for a simple utilization of conventional parameter extraction methods. Therefore the gate-voltage-dependent hole mobility and the source/drain parasitic resistance in the pentacene transistors were evaluated with the aid of device simulation accounting for Schottky contact with a thermionic field emission model. The hole mobility in the channel region shows smaller values with shorter channel length even after removing the influence of Schottky barrier, suggesting that some disordered semiconductor layers with low carrier mobility exist near the contact electrode. This experimental data analysis with the simulation enables us to discuss and understand in detail the operation mechanism of bottom-gate, bottom-contact transistors by considering properly each process of charge carrier injection, carrier flow near the contact region, and actual channel transport.     

Room-temperature CW operation of InGaAsP lasers on Si fabricated by wafer bonding

1.3-/spl mu/m InGaAsP-InP lasers have been successfully fabricated on Si substrates by wafer bonding with heat treatment at 400/spl deg/C. A pressure of 4 kg/cm/sup 2/ has been applied on the wafers before the heat treatment and this pressure application has enabled us to achieve bonding strength required for the device fabrication even when the bonding temperature is as low as 400/spl deg/C. Room-temperature continuous-wave operation with threshold current of 49 mA has been achieved for 7-/spl mu/m-wide mesa lasers.     

Growth of (111) HgCdTe on (100) Si by MOVPE using metalorganic tellurium adsorption and annealing

(lll)B CdTe layers free of antiphase domains and twins were directly grown on (100) Si 4°-misoriented toward<011> substrates, using a metalorganic tellurium (Te) adsorption and annealing technique. Direct growth of (lll)B CdTe on (100) Si has three major problems: the etching of Si by Te, antiphase domains, and twinning. Te adsorption at low temperature avoids the etching effect and annealing at a high temperature grows single domain CdTe layers. Te atoms on the Si surface are arranged in two stable positions, depending on annealing temperatures. We evaluated the characteristics of (lll)B CdTe and (lll)B HgCdTe layers. The full width at half maximum (FWHM) of the x-ray double crystal rocking curve (DCRC) showed 146 arc sec at the 8 |im thick CdTe layers. In Hg_1−xCd_xJe (x = 0.22 to 0.24) layers, the FWHMs of the DCRCs were 127 arc sec for a 7 (im thick layer and 119 arc sec for a 17 (im thick layer. The etch pit densities of the HgCdTe were 2.3 x 106 cm2 at 7 ^m and 1.5 x 106 cm-2 at 17 um.     

Direct growth of CdTe on (100), (211), and (111) Si by metalorganic chemical vapor deposition

CdTe epilayers were grown directly on (100), (211), and (111) silicon substrates by metalorganic chemical vapor deposition (MOCVD). The crystallinity and the growth orientation of the CdTe film were dependent on the surface treatment of the Si substrate. The surface treatment consisted of exposure of the Si surface to diethyltelluride (DETe) at temperatures over 600°C prior to CdTe growth. Direct growth of CdTe on (100) Si produced polycrystalline films whereas (lll)B single crystals grew when Si was exposed to DETe prior to CdTe growth. On (211) Si, single crystal films with (133)A orientation was obtained when grown directly; but produced films with (211)A orientation when the Si surface was exposed to DETe. On the other hand, only (lll)A CdTe films were possible on (111) Si, both with and without Te source exposure, although twinning was increased after exposure. The results indicate that the exposure to a Te-source changes the initial growth stage significantly, except for the growth on (111) Si. We propose a model in which a Te atom replaces a Si atom that is bound to two Si atoms.     

Automatic Tuning System for Integrator-Based Continuous-Time Filters

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.