Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

High Rate Data Synchronization in GALS SoCs

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner     

All-optical seed pulse extraction for packet synchronization based on self-induced effects in a vertical-cavity semiconductor gate

Self-induced effects in a passive polarization-independent vertical-cavity semiconductor gate are investigated numerically and experimentally. We demonstrate all-optical seed-pulse extraction for synchronization of differential phase-shift keying and ON-OFF keying packets at 10 Gb/s. Our results provide evidence that vertical-cavity gates, exploiting saturable absorption in semiconductor quantum-wells, exhibit attractive performances in terms of efficiency, power consumption, and polarization independency.     

The colored revolution of bioimaging

This paper provides an overview of the main aspects of modern fluorescence microscopy. It covers the principles of fluorescence and highlights the key discoveries in the history of fluorescence microscopy. The paper also discusses the optics of fluorescence microscopes and examines the various types of detectors. It also discusses the signal and image processing challenges in fluorescence microscopy and highlights some of the present developments and future trends in the field.     

Smooth profile generation for a tile printing machine

In this paper a digital filter is proposed for the generation of smooth set points for motion control systems. The proposed nonlinear filter produces profiles with bounded velocity and acceleration starting from rough reference signals (steps and ramps). An actual implementation of the filter for a tile printing machine is presented and experimental results are reported.     

Development and commissioning of decision support tools for sewerage management.

Managing sewerage systems is a highly complex task due to the dynamic nature of the facilities. Their performance strongly depends on the know-how applied by the operators. In order to define optimal operational settings, two decision support tools based on mathematical models have been developed. Moreover, easy-to-use interfaces have been created as well, aiding operators who presumably do not have the necessary skills to use modelling software. The two developed programs simulate the behaviour of both wastewater treatment plants (WWTP) and sewer network systems, respectively. They have essentially the same structure, including raw data management and statistical analysis, a simulation layer using the application programming interface of the applied software and a layer responsible for the representation of the obtained results. Four user modes are provided in the two software including the simulation of historical data using the applied and novel operational settings, as well as modes concerning prediction of possible operation periods and updates. Concerning the WWTP software, it was successfully installed in Nantes (France) in June 2004. Moreover, the one managing sewer networks has been deployed in Saint-Malo (France) in January 2005. This paper presents the structure of the developed software and the first results obtained during the commissioning phase.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

High-frequency analysis of the Ellipticus antenna

Efficient numerical solution techniques have been developed and used to examine the electromagnetic fields that can be developed in the working volume of the CW Ellipticus antenna operated at frequencies from 100 kHz to 1 GHz. An exponentially tapered transition section is designed to obtain the desired illumination pattern in the working volume. The input transition section is needed for impedance matching and to drive efficiently the Ellipticus antenna. A parametric study is performed to ascertain the performance of the Ellipticus antenna for frequencies up to 1 GHz