SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

Na2O.CaO.2P2O5玻璃析晶初期的分形

报道了Ｎａ２Ｏ．ＣａＯ．２Ｐ２Ｏ３玻璃析晶期间的相变过程，认为分形是玻璃分相和析晶期间的亚微观结构变化，其分形合维数为１．８０５±０．００１。     

不同形态硫化物对稠油热采硫化氢产生的贡献分析

随着开发的不断进行,稠油热采过程中硫化氢的产生量不断增加,尤其是在蒸汽驱区块硫化氢的产生量呈现急剧增加的趋势,严重影响了稠油热采区块的安全生产。为了进一步明确稠油热采过程中硫化氢的产生原因,对稠油热采过程中的含水量、处理温度和处理时间等因素进行了分析。研究结果表明,目标稠油在含水量为20%,处理温度为260℃,处理时间为48 h的条件下,不同形态的硫化物能够最大程度地转化为硫化氢;硫醇硫和硫醚硫在稠油热采条件下对硫化氢的产生有贡献,噻吩硫在稠油热采条件下对硫化氢的产生无贡献。分析不同形态硫化物对稠油热采硫化氢产生的贡献,可为高含硫区块的开发及制定相应的防治措施提供技术支持。     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

Thermodynamic perfectibility based analysis of energy-efficiency standards for air conditioning products in China

There are presently different types of air conditioning products in China such as room air conditioners, variable speed room air conditioners, unity air conditioners, multi-connected air-condition (heat pump) unit, chilled water air conditioning systems. For these air conditioning products, evaluation indexes have been created, respectively including energy efficiency ratio (EER), coefficient of performance (COP), seasonal energy efficiency ratio (SEER) and integrated part load value (IPLV), and their energy efficiency standards have been established. Based on thermodynamic perfectibility, this paper makes the compatible analysis of the energy efficiency and thermodynamic perfectibility gradient of energy efficiency standards for different air conditioning products. According to testing conditions of evaluation indexes, these air conditioning products are classified into two groups, the standard rating conditions group (EER, COP) and the variable working condition group (SEER, IPLV). The results show the thermodynamic perfectibility of different air conditioning products grade as the same level for energy efficiency standards in each group differ from one another. Besides, the average thermodynamic perfectibility gradient of energy efficiency levels for air conditioning product in the standard rating conditions group is basically the same, and that of variable speed room air conditioners and multi-connected air-condition (heat pump) unit are the highest and lowest, respectively.     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

多功能酸洗缓蚀抑雾剂的后效性能研究

本文采用线性极化法测定了多种酸洗体系加入多功能酸洗缓蚀抑雾剂CQH-2前后的极化电阻，研究了缓蚀剂的缓蚀效率随时间的变化关系，以评定CQH-2缓蚀剂的后效性能。结果表明：CQH-2在多种酸洗体系中后效性能良好，仅在铝的酸洗中，缓蚀率和后效性能均较差，加入吖啶后，缓蚀率和后效性能都显著提高。     

A High Performance Sub-100nm Nitride/Oxynitride Stack Gate Dielectric CMOS Device with Refractory W/TiN Metal Gates

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

PIRAY纤维机织物综合性能评价

分析PIRAY纤维机织物的导湿性、透湿性、透气性、折痕回复性、耐磨性及拉伸断裂强力,并进行综合性能评价。通过测试3种纯纺PIRAY纤维织物与6种其他组织规格相近的棉、涤纶及混纺织物的芯吸高度、透湿量、透气量、折痕回复角、质量损失率、断裂强力,应用模糊数学综合评判方法进行对比分析,结果表明:PIRAY纤维织物的透湿性、透气性、折皱回复角、耐磨性和强伸性等综合性能优于其他织物,芯吸效应明显优于涤纶纤维织物,PIRAY纤维织物还具有良好的防紫外线性能。