Evaluation of Qbd for electrons tunneling fromthe Si/SiO2 interface compared to electron tunneling from thepoly-Si/SiO2 interface

Electrical time-to-breakdown (TTB) measurements have shown the charge to breakdown Q_bd of gate oxide capacitors fabricated on n-type well (n-well) substrates always to be higher than that of capacitors on p-type well (p-well) substrates on the same wafer when both are biased into accumulation under normal test conditions. Here the authors correlate the higher n-well Q_bd to smooth capacitor oxide/substrate interfaces and minimized grain boundary cusps at the poly-Si gate/oxide interfaces, confirming that Fowler-Nordheim tunneling is the dominant current conduction mechanisms through the oxide. They correlate higher Q_bd to higher barrier height for a given substrate type and observe that the slope of the barrier height versus temperature plot is lower for both p-well and n-well cases with electrons tunneling from the silicon substrate. This is attributed to surface roughness at the poly-Si gate/SiO₂ interface. A poly-Si gate deposition and annealing process with clean, smooth oxide/substrate interfaces will improve the p-well breakdown characteristics and allow higher Q_bd to be achieved     

Point of utilization power quality study results

A wide variety of electromagnetic phenomena occurring on AC power lines has been held responsible for literally billions of dollars per year in lost revenue. Information related to actual probability of occurrence of these power line deviations is presently limited. This paper describes the results of four years of point of utilization power quality monitoring at 112 North American locations. A quantity of 1057 site months of data collected between 1990 and 1994 was used in this assessment. The data indicate that the numbers of events occurring at typical locations may range from almost none, to thousands per month. The analysis results characterize several aspects of power quality related to the occurrence of low RMS events, high RMS events, transient events, and power interruptions (outages)     

Study of Desorption and Adsorption During Grain Aeration

One requirement in designing and operating and operating system is to minimize the moisture change in stored grain. Moisture transfer during the aeration process is generally believed to be caused by the partial pressure difference between water in grain and water in air (P₃-P₄). A mathematical model was developed for rough rice, which predicts the partial pressure difference under various grain and ambient conditions. Observations of moisture change over 10 aeration tests confirmed the good correlation between sorption phenomena and partial pressure differences. Studies indicated that air relative humidity, air temperature, grain temperature and grain moisture are significant factors influencing the partial pressure differences and, thus, affecting     

Structured genetic algorithm for robust H∞ controlsystems design

A structured genetic algorithm (SGA) approach is developed for robust controller design based on the concept of an H^∞ loop-shaping technique and the method of inequalities. Such an SGA is capable of simultaneously searching the orders and coefficients of the precompensator and postcompensator for the weighted plant. It is, therefore, not necessary to predefine the order of compensators as in usual practice. A multiple objective ranking approach is also incorporated so that the design criteria of extreme plants can be easily achieved. The effectiveness of such a technique is illustrated by a high-purity distillation column design example     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

Genetic algorithms: concepts and applications [in engineeringdesign]

This paper introduces genetic algorithms (GA) as a complete entity, in which knowledge of this emerging technology can be integrated together to form the framework of a design tool for industrial engineers. An attempt has also been made to explain “why” and “when” GA should be used as an optimization tool     

Analysis of thin walled structures using the boundary element method

In this article the direct boundary element formulations of stretching and bending plate problems are combined together to solve thin walled structures and other similar frames. The final system is obtained by assuming each individual plane structural element as a subregion. After the necessary transforms of these equations they can be combined together taking into account the displacement compatibility and equilibrium conditions.