Purification and identification of antioxidant peptide from black pomfret, <Emphasis Type=Italic>Parastromateus niger</Emphasis> (Bloch, 1975) viscera protein hydrolysate

To utilize fish waste, black pomfret, Parastromateus niger viscera was analysed for its proximate and amino acid composition followed by hydrolysis using various proteases to extract antioxidant peptide. Antioxidant activities of the crude hydrolysate was evaluated using DPPH (54%), metal chelating (78.6%) at a concentration of 1 mg/mL, whereas the reducing power assay was done with different concentration (0.5–2.5 mg/mL) and the activity also increased with increasing concentration (0.021–0.068). Furthermore, the hydrolysate was purified by diethylaminoethyl (DEAE) ion-exchange and Sephadex G-25 gel filtration chromatography. Finally, the purified peptide had a mass of 701.9 Da, and the amino acid sequence was identified as Ala-Met-Thr-Gly-Leu-Glu-Ala using electrospray ionization-tandem mass spectrometry (ESI-MS/MS). Moreover, the protection ability of the peptide toward hydroxyl radical-induced oxidative DNA damage and inhibiting lipid peroxidation was evaluated and compared with natural antioxidant α-tocopherol.     

Dielectric properties of iron doped calcium copper titanate,CaCu<Subscript>3</Subscript>Ti<Subscript>3.9</Subscript>Fe<Subscript>0.1</Subscript>O<Subscript>12</Subscript> ceramic

Dielectric properties of iron doped CaCu₃Ti₄O₁₂ (CCTO), viz. CaCu₃Ti_3.9Fe_0.1O₁₂ (CCTFO) prepared by a novel semi-wet route have been investigated. X-ray diffraction of powder sintered at 900 °C show formation of single phase solid solution. Energy dispersive X-ray spectroscopy (EDX) confirmed the presence of CuO rich phase at grain boundaries of CCTFO. Nature of dielectric relaxation observed above room temperature is studied using complex plane impedance analysis and modulus spectroscopy. It has been found that out of the two relaxations reported earlier above room temperature, one occurring at lower temperature is due to grainboundaries interfacial polarization.     

Some system design considerations for a high switching frequency PWM inverter

A sinusoidal PWM inverter is required to faithfully reproduce the control waveforms at the output with minimum distortion. This paper presents some design considerations for such an inverter. The choice of switching frequency is the main criterion which affects the output voltage harmonic distortion at high switching frequencies. This paper shows that there exists an optimum switching frequency above which the output harmonic distortion becomes more visible. The dead time generator circuit for a low cost inverter and effect of driver circuits on the output waveform are discussed. Experimental results from laboratory models are presented.     

On the implementation of a real-time information security architecture in frequency domain

This paper presents the real-time implementation of a watermarking-based information security architecture in frequency domain. The scheme emphasises on the human visual system (HVS)-supported watermarking approach using wavelet-lifting technique. In addition to HVS, image registration algorithm is also introduced in order to increase the resiliency as well as the security of the estimated recovered watermark image. The algorithmic steps with optimisation considerations about the real-time implementation on TMS320CDSK6416/6713 fixed/floating point digital signal processor are also projected.     

Triple Band Annular Ring Loaded Stacked Circular Patch Microstrip Antenna

In this paper a novel structure of annular ring loaded stacked circular patch microstrip antenna is theoretically analysed to observe various parameters such as return loss, input impedance, gain, directivity and radiation pattern. It is found that antenna possess three band of operation which signify the compactness and multiband operation of antenna. The antenna is resonating at three operating frequencies 1.720, 2.950, 3.060 GHz. The proposed theory is verified by simulation using Ansoft’s HFSS and theoretical results are in good agreement with simulated results. The antenna is useful for multi-services operations such as WLAN, GSM, UMTS, and WiMAX services.     

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Advanced nanometer technologies have led to a drastic increase in operational frequencies resulting in the performance of circuits becoming increasingly vulnerable to timing variations. The increasing process spread in advanced nanometer nodes poses considerable challenges in predicting post-fabrication silicon performance from timing models. Thus, there is a great need to qualify basic building structures on silicon in terms of critical parameters before they could be integrated within a complex System-on-Chip (SoC). The work of this paper presents a configurable circuit and an associated power-aware at-speed test methodology for the purpose of qualifying basic standard cells and complex IP structures to detect the presence of timing faults. Our design has been embedded within test-chips used for the development of the 28 nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The relevant silicon results and analysis validate the proposed power-aware test methodology for qualification and characterization of IPs and provide deeper insights for process improvements.