Real-Time monitoring of III-V molecular beam epitaxial growth using spectroscopic ellipsometry

We report the real-time monitoring of monolayer thickness changes in AlAs and GaAs layer growth on rotating GaAs substrates using spectroscopic ellipsometry (SE). A phase-modulated spectroscopic ellipsometer was integrated with a III-V MBE system by triggering spectral acquisition synchronously with substrate rotation. Absolute thickness accuracy was verified using ex situ SE measurement. Reasonable agreement was also obtained between in situ growth rate measurements by SE and reflection high energy electron diffraction. The precision and speed of this method appears suitable for real-time control of quantum devices, such as resonant-tunneling diodes.     

Experimental Evidence for Formation of Ni-Al Compound in Flip-Chip Joints Under Current Stressing

The materials interactions on the under bump metallization (UBM) side of flip-chip solder joints during current stressing were studied by using high-resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM). Flip-chip solder joints with sputtered Al/Ni(V)/Cu UBM were subjected to current stressing at an ambient temperature of 150°C. It was found that a layer of Ni-Al phase, presumably NiAl₃ according to energy-dispersive x-ray spectroscopy (EDX) measurements, was observed at the Al/Ni(V) interface. In addition, evidence for the formation of a nonconductive oxide layer at the NiAl₃/Ni(V) interface was observed. This nonconductive oxide layer was responsible for diverting electron current away from the porous region.     

GaAsSb/InAlAs PA DHBTs Grown by Production MBE

The epi material growth of GaAsSb based DHBTs with InAlAs emitters are investigated using a 4 × 100mm multi-wafer production Riber 49 MBE reactor fully equipped with real-time in-situ sensors including an absorption band edge spectroscope and an optical-based flux monitor. The state-of-the-art hole mobilities are obtained from 100nm thick carbon-doped GaAsSb. A Sb composition variation of less than ± 0.1 atomic percent across a 4 × 100mm platen configuration has been achieved. The large area InAlAs/GaAsSb/InP DHBT device demonstrates excellent DC characteristics,such as BVCEO＞6V and a DC current gain of 45 at 1kA/cm2 for an emitter size of 50μm × 50μm. The devices have a 40nm thick GaAsSb base with p-doping of 4. 5 × 1019cm-3 . Devices with an emitter size of 4μm × 30μm have a current gain variation less than 2% across the fully processed 100mm wafer. ft and fmax are over 50GHz,with a power efficiency of 50% ,which are comparable to standard power GaAs HBT results. These results demonstrate the potential application of GaAsSb/InP DHBT for power amplifiers and the feasibility of multi-wafer MBE for mass production of GaAsSb-based HBTs.     

Effect of Cu concentration on the reactions between Sn-Ag-Cu solders and Ni

The reaction between the Sn-Ag-Cu solders and Ni at 250°C for 10 min and 25 h was studied. Nine different Sn-Ag-Cu solders, with the Ag concentration fixed at 3.9 wt.% and Cu concentrations varied between 0.0–3.0 wt.%, were used. When the reaction time was 10 min, the reactions strongly depended on the Cu concentration. At low-Cu concentrations (≦0.2 wt.%), only a continuous (Ni_1−xCu_x)₃Sn₄ layer formed at the interface. When the Cu concentration increased to 0.4 wt.%, a continuous (Ni_1−xCu_x)₃Sn₄ layer and a small amount of discontinuous (Cu_1−yNi_y)₆Sn₅ particles formed at the interface. When the Cu concentration increased to 0.5 wt.%, the amount of (Cu_1−yNi_y)₆Sn₅ increased and (Cu_1−yNi₆)₆Sn₅ became a continuous layer. Beneath this (Cu_1−yNi_y)₆Sn₅ layer was a very thin but continuous layer of (Ni_1−xCu_x)₃Sn₄. At higher Cu concentrations (0.6–3.0 wt.%), (Ni_1−xCu_x)₃Sn₄ disappeared, and only (Cu_1−yNi_y)₆Sn₅ was present. The reactions at 25 h also depended strongly on the Cu concentration, proving that the strong concentration dependence was not a transient phenomenon limited to a short reaction time. The findings of this study were rationalized using the Cu-Ni-Sn isotherm. This study shows that precise control over the Cu concentration in solders is needed to produce consistent results.     

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $hbox{TaN/HfO}_{2}$ Gate Stack Structure

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO₂ gate stack is demonstrated for the first time. The devices of low threshold voltage V_TH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility mu_FE ~ 240 cm²/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO₂ gate dielectric with the effective oxide thickness of 5.12 nm.     

Characterization and modeling of on-chip spiral inductors for Si RFICs

The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.     

Very low noise RF nMOSFETs on plastic by substrate thinning and wafer transfer

A very low minimum noise figure (NF/sub min/) of 1.2 dB and a high associated gain of 12.8 dB at 10 GHz were measured for six-finger, 0.18-/spl mu/m radio frequency (RF) metal-oxide semiconductor field-effect transistors mounted on insulating plastic following substrate-thinning (/spl sim/30 /spl mu/m) and wafer transfer. Before this process, the devices had a slightly better RF performance of 1.1-dB NF/sub min/ and a 13.7-dB associated gain. The small RF performance degradation of the active transistors transferred to plastic shows the potential of integrating electronics onto plastic.     

An investigation into the effects of probing and wire bonding stress on the reliability of BOAC

This work describes two types of low stress bonding over active circuit (BOAC) structures applying a finite element analysis. The advantage of improving the chip area utility of the BOAC design is approximately 150–180 μm for each dimension. A 0.13 μm 2 Mb high-speed SRAM with fluorinated silicate glass (FSG) low-k dielectric was combined with these two BOAC structures as the test vehicles to evaluate the impact of the probing and wire bonding stress on the reliability. Initially, a cantilevered probe card was applied to probe the BOAC pads using the typical and the worse probing conditions. Before and after the circuits probing (CP1 and CP2) the experimental results were compared, including the 2 Mb high-speed SRAM yield and wafer bit map data. The difference between the CP1 and CP2 results were negligible for all probing split cells. Next, the cross-section of the BOAC pad under the probing area was investigated following the worst probing condition. In addition, the BOAC pads evaluate the bondability, including the use of ball shear, wire pull and cratering tests. Moreover, all BOAC packaging samples underwent reliability tests, including HTOL, TCT, TST, and HTST. All the bondability and reliability tests passed the criteria for both proposed BOAC structures. Finally, the immunity level of both proposed BOAC pads, for ESD-HBM (human body mode) and ESD-MM (machine mode), differed slightly from the normal pads. No performance degradation was detected. Accordingly, this work shows that both proposed BOAC structures can be used to improve the active chip area utility or save the chip area.     

Parasitic extraction: current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given     

A Fully Integrated 0.13- μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer

A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13-mum CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the inductors and using a small-area oscillator has reduced both the parasitic magnetic and substrate coupling, allowing single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant reduction in die area was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL passive loop filter to reduce the equivalent VCO tuning gain. This improves PLL noise and spur performance and allows the on-chip integration of the loop filter. The digital low-IF tuner allows the use of a discrete step AGC loop that results in lower noise figure and higher linearity. Automatic signal path gain and bandwidth digital calibration was realized using replica ring oscillators. Tuner specifications include: 90 dB gain range, 10 dB noise figure at max gain, +25dBm IIP3 at min gain, 1.3deg rms integrated phase noise, <-50dBc spurs, 0.5-W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm² die area