Hardware Implementation of Enhancement Embedded Reduced Runtime Recovery Algorithm for Compressively Sensed Images

Compressed sensing is based on the principle that, through optimization, the sparsity of a signal can be exploited to recover it from fewer samples than required by the criterion. In compressed sensing, data is compressed and converted into fewer measurements and transmitted through wireless channel which is reconstructed at the receiver. Since very few samples are used for reconstruction, there are possibilities of degradation in quality of reconstruction. Unlike traditional methods, enhancement can now be done using the recent technique of compressed sensing by embedding image enhancement techniques like edge detection, histogram, filtering and their combinations with CS recovery procedure. This work proposes such a method by binding the image enhancement techniques along with the compressed sensing process. Filter of Gaussian filter (FGF), a combinational filter proposed in this study enables an increase in PSNR of 1 dB when compared to other filtering techniques besides using least number of measurements and maintaining minimum time consumption. The runtime difference with and without the FGF is ~?3 s, which is affordable even in hardware with minimum specifications. Real time experimentation of embedded enhancement CS was carried out in WINGZ board to prove the feasibility of enhanced recovery process with lower end hardware.     

Mapping of Lattice Strain in 4H-SiC Crystals by Synchrotron Double-Crystal X-ray Topography

The presence of lattice strain in n-doped 4H-SiC substrate crystals grown by a physical vapor transport method can strongly influence the performance of related power devices that are fabricated on them. Information on the level and the variation of lattice strain in these wafer crystals is thus important. In this study, a non-destructive method is developed based on synchrotron double-crystal x-ray topography to map lattice strains in 4H-SiC wafers. Measurements are made on two 4H-SiC substrate crystals—one is an unprocessed commercial wafer while the other was subject to a post-growth high-temperature heat treatment. Maps of different strain components are generated from the equi-misorientation contour maps recorded using synchrotron monochromatic radiation. The technique is demonstrated to be a powerful tool in estimating strain fields in 4H-SiC crystals. Analysis of the strain maps also shows that the normal strain components vary much more significantly than do the shear/rotation components, indicating that lattice dilation/compression rather than lattice tilt is the major type of deformation caused by both the incorporation of nitrogen dopants and the nucleation of basal plane dislocations.     

Effects of High-Pressure High-Temperature Sintering on the Band Gap and Thermoelectric Properties of PbSe

In this study, PbSe bulk samples were prepared by a high-pressure high-temperature (HPHT) sintering technique, and the phase compositions, band gaps and thermoelectric properties of the samples were systematically investigated. The sintering pressure exerts a significant influence on the preferential orientation, band gap and thermoelectric properties of PbSe. With increasing pressure, the preferential orientation decreases, mainly due to the decreased crystallinity, while the band gap first decreases and then increases. The electrical conductivity and power factor decrease gradually with increasing pressure, mainly attributed to the decreased carrier concentration and mobility. Consequently, the sample prepared by 2 GPa shows the highest thermoelectric figure-of-merit, ZT, of 0.55 at ～ 475 K. The ZT of the HPHT-sintered PbSe could be further improved by properly doping or optimizing the HPHT parameters. This study further demonstrates that the sintering pressure could be another degree of freedom to manipulate the band structure and thermoelectric properties of materials.     

Robust Scene-Based Digital Video Watermarking Scheme Using Level-3 DWT: Approach,Evaluation, and Experimentation

This paper presents a robust digital video-watermarking system for copyright and copy protection. The proposed method applies the combination of discrete wavelet transform (DWT) and scene-change-detector. For better understanding, this approach can be presented in the form of four stages. The first stage is finding the frame where the watermark is to be inserted. The analysis of watermarking using the level-3 decomposition of LL subband withDWTis described in the second stage. Transparency and the robustness have been analyzed under fifteen different attacks in the third stage. Improvement in the robustness and transparency, as compare to watermarking using different levels of LL subband is calculated in terms of the normalized correlation and the structural similarity index in the fourth stage. The experimental result reveal that the proposed method yields the extracted watermark image and watermarked video of good quality and can sustain different image processing, JPEG compression and geometrical attacks. Empirical results prove the improvement in the performance as the decomposition level increases from level-1 to level-3. Comparative analysis with the existing schemes proves the improved robustness, better imperceptibility and the reduced computational time of the proposed scheme.     

ACS-Fed e-Shaped Dual Band Uniplanar Printed Antenna for Modern Wireless Communication Applications

A printed small size (12×16.5 mm) ACS-fed e-shaped uniplanar antenna is proposed for dual band applications. The multiband operating characteristics have been achieved by integrating e-shaped radiating strips to the 50ΩACSfeed line. Two simultaneously operating wide bands have been generated by using optimized radiating branch strips for the multiband applications. For obtaining size reduction and wider impedance bandwidth, e-shaped meandered elements are chosen in the design. The proposed design features the bandwidth (VSWR < 2, reflection coefficient below–10 dB) of 100 MHz in 2.4–2.5 GHz, and 2100MHzin 4.0–6.1 GHz. The developed multiband antenna can be useful for several wireless communication applications, such as 2.4 GHz Bluetooth/RFID,WLAN(2.4/5.2/5.8 GHz), WiMAX (5.5 GHz), US public safety band (4.9 GHz), ISM band, radio frequency energy harvesting and internet of things (IoT) applications.     

<Emphasis Type="Italic">μ</Emphasis>DTNSec: a security layer with lightweight certificates for Disruption-Tolerant Networks on microcontrollers

In Delay/Disruption-Tolerant Networks, man-in-the-middle attacks are easy: due to the store-carry-forward principle, an attacker can simply place itself on the route between source and destination to eavesdrop or alter bundles. This weakness is aggravated in networks, where devices are energy-constrained but the attacker is not. To protect against these attacks, we design and implement μDTNSec, a security layer for Delay/Disruption-Tolerant Networks on microcontrollers. Our design establishes a public key infrastructure with lightweight certificates as an extension to the Bundle Protocol. It has been fully implemented as an addition to μDTN on Contiki OS and uses elliptic curve cryptography and hardware-backed symmetric encryption. In this enhanced version of μDTNSec, public key identity bindings are validated by exchanging certificates using neighbor discovery. μDTNSec provides a signature mode for authenticity and a sign-then-encrypt mode for added confidentiality. Our performance evaluation shows that the choice of the curve dominates the influence of the payload size. We also provide energy measurements for all operations to show the feasibility of our security layer on energy-constrained devices. Because a high quality source of randomness is required, we evaluated the random number generators by the AT86RF231 radio, its successor AT86RF233, and one based on the noise of the A/D converter. We found that only AT86RF233 provides the required quality.     

Effects of solid-state annealing on the interfacial intermetallics between tin-lead solders and copper

The interfacial intermetallics between Cu and solder were studied for four Sn-Pb compositions at the annealing temperatures of 125°C, 150°C, and 175°C for up to 30 days. The η-phase (Cu₆Sn₅) layer formed during reflow continues to grow during annealing. An additional layer of ɛ-phase (Cu₃Sn) forms at the η/Cu interface after an incubation annealing time. The thickness results fit a power-law relationship against time with average exponents 0.69 and 0.44 for the η phase and the ɛ phase, respectively. On prolonged annealing, the proportions of the individual phases in the total layer reach a steady state.     

A fast-settling charge-pump PLL with constant loop bandwidth

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the \(\Delta \varSigma\) modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump \(Icp\) is programmed not only to compensate the variation of voltage-controlled oscillator gain \(Kvco\), but also for adapting to the change of divider ratio \(N_{m}\). This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 µm CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is ? 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized \(\left( {Icp*Kvco} \right)/N_{m}\) which is equivalent to the variation of PLL loop bandwidth ranges from ? 6 to 6%.     

On the design of highly linear CMOS digitally programmable operational transconductance amplifiers for low and high-frequency applications

This paper proposes a novel highly linear digitally programmable fully differential operational transconductance amplifier (DPOTA) circuit. Two versions of the proposed DPOTA structure are designed. The first version is optimized for high-frequency operation with current division networks designated to 3-bit control code words. On the other hand, the second version is optimized for low-frequency operation with 4-bit control code words. The third-order harmonic distortion (HD3) of the first DPOTA version remains below ? 66 dB up to 0.4 V differential input voltage at 10 MHz frequency. The second DPOTA version achieved HD3 of ? 70 dB with an amplitude of 20 mV_p–p and at 100 Hz frequency. The proposed circuits are designed and simulated in 90 nm CMOS model, BSIM4 (level 54) under a balanced 1.2 V supply voltage.