Repeated Price Search

Consumers check few sites in online purchases. Previous research and experiments we perform demonstrate that consumers can not calculate the optimal strategy for price search. They use heuristics whose performance is better than random and less than optimal. To investigate online price search performance we survey student online textbook purchases. Students achieve good performance because they start with a good strategy and online market organization of marketplace and meta-search sites. An important factor is that algorithms at sites searched perform calculations that reduce the computational complexity of the search.     

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library

We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, due to the fact that it does not provide adequate support for the specialized architectural features of DSPs via machine-dependent code optimizations. Thus, designers often program the embedded software in assembly, a very time-consuming task. In order to increase productivity, compilers must be developed that are capable of generating high-quality code for DSPs. The compilation process must also be made retargetable, so that a variety of DSPs may be efficiently evaluated for potential use in an embedded system. We present a retargetable compilation methodology that enables high-quality code to be generated for a wide range of DSPs. Previous work in retargetable DSP compilation has focused on complete automation, and this desire for automation has limited the number of machine-dependent optimizations that can be supported. In our efforts, we have given code quality higher priority over complete automation. We demonstrate how by using a library of machine-dependent optimization routines accessible via a programming interface, it is possible to support a wide range of machine-dependent optimizations, albeit at some cost to automation. Experimental results demonstrate the effectiveness of our methodology, which has been used to build good-quality compilers for three fixed-point DSPs. This revised version was published online in July 2006 with corrections to the Cover Date.     

Solar Energy System with Digital Controller for Grid Connected Systems

The solar photovoltaic (PV) module output voltage changes according to the variation of light intensity and temperature. This paper presents the implementation of an automatic digital controller of a DC-DC boost converter without batteries for a solar cell module by using a peripheral interface controller, which forms a closed loop, to control the ON-OFF period of the switching pulse. The output of DC-DC converter is maintained by automatically increasing or decreasing the pulse width. To produce the pulse width modulation (PWM), the microcontroller is programmed according to the required duty cycle for the power switch. The PWM ON period is increased with the decrease in the PV voltage and vice-versa. The input voltage to the inverter is maintained constantly and is converted into an AC signal by using the metal-oxide-semiconductor field effect transistor (MOSFET) H-bridge operated in the sinusoidal pulse width modulation mode by using a PIC (peripheral interface controller) microcontroller. The generated AC signal can be connected to the AC grid or to the AC load. The simulated results by using Proteus 8 and hardware implemented results verify the effectiveness of the proposed controller.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

Optimum design of reliable systems for specified life cycle cost

A new procedure for design for optimum reliability is given using a maximum life cycle cost constraint. Various life cycle cost vs reliability models are used for the purpose. The problem is treated for a series reliability structure. A numerical example is given to illustrate the procedure. The work establishes a firm quantitative footing for optimum life cycle cost design of reliable systems. In a sense it is revolutionary in the design-to-cost philosophy so often encountered in reliability design.     

Synthesis and characterization of organo‐soluble poly(ether ether ketone)s and poly(ether ether ketone ketone)s containing pendant pentadecyl chains

Poly(ether ether ketone)s and poly(ether ether ketone ketone)s containing pendant pentadecyl chains were synthesized by polycondensation of each of the two bisphenol monomers viz, 1,1,1‐[bis(4‐hydroxyphenyl)‐4′‐pentadecylphenyl]ethane and 1,1‐bis(4‐hydroxyphenyl)‐3‐pentadecyl cyclohexane with activated aromatic dihalides namely, 4,4′‐difluorobenzophenone, and 1,3‐bis(4‐fluorobenzoyl)benzene in a solvent mixture of N,N‐dimethylacetamide and toluene, in the presence of anhydrous potassium carbonate. Polymers were isolated as white fibrous materials with inherent viscosities and number average molecular weights in the range 0.70–1.27 dL g^?1 and 76,620–1,36,720, respectively. Poly(ether ether ketone)s and poly(ether ether ketone ketone)s were found to be soluble at room temperature in organic solvents such as chloroform, dichloromethane, tetrahydrofuran, and pyridine and could be cast into tough, transparent, and flexible films from their solutions in chloroform. Wide angle X‐ray diffraction patterns exhibited a broad halo at around 2θ = ～ 19° indicating that the polymers containing pentadecyl chains were amorphous in nature. In the small‐angle region, diffuse reflections of a typically layered structures resulting from the packing of pentadecyl side chains were observed. The temperature at 10% weight loss, obtained from TG curves, for poly(ether ether ketone)s and poly(ether ether ketone ketone)s were in the range 416–459°C, indicating their good thermal stability. A substantial drop in glass transition temperatures (68–78°C) was observed for poly(ether ether ketone)s and poly(ether ether ketone ketone)s due to “internal plasticization” effect of flexible pendant pentadecyl chains. © 2011 Wiley Periodicals, Inc. J Appl Polym Sci, 2011