Temperature dependence of signal gain in Er3+-dopedoptical fiber amplifiers

Temperature-dependent signal gain characteristics at signal wavelengths of 1.536 and 1.552 μm in Er³⁺-doped optical fibers with a temperature range of -40 to 80°C are reported for 0.98 and 1.48 μm pumping. The temperature dependences of signal gain strongly depend on fiber length, pump wavelength, and signal wavelength. The fiber length at which signal gain temperature insensitivity occurs is found for the amplification of a 0.98-μm-pump-1.536-μm-signal, a 0.98-μm-pump-1.552-μm-signal, and a 1.48-μm-pump-1.536-μm-signal. It is confirmed theoretically that the temperature dependences result from linear changes in the fluorescence, and absorption cross sections at the signal and pump wavelengths, and a shift in the effective pump wavelength     

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-pointnoise reduction coding I/O

A 32-b 500-MHz 4-1-1-1 operation 4-Mb pipeline burst cache SRAM has been developed. In order to achieve both high bandwidth operation and short latency operation, we developed the following technologies: 1) a prefetched pipeline-burst scheme with double late-write buffers, 2) gate size reduction and a bit-line equalization by source resetting, 3) point-to-point bidirectional coding I/O's to reduce bus noise and power consumption, and 4) a three-level metal 0.25-μm CMOS process technology with six transistor memory cells     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

Nano-area electron diffraction pattern reconstructed from three-dimensional Fourier spectrum.

A method to obtain a nano-area electron diffraction pattern in transmission electron microscopy (TEM) was proposed, based on three-dimensional (3D)) image formation theory. This method allows us to reconstruct an electron diffraction pattern from a 3D Fourier spectrum of high-resolution through-focus images. As a test case, an electron diffraction pattern from a tilted Si single crystal was reconstructed using the proposed method and compared with the conventional selected-area electron diffraction pattern. The intensity distribution of the reconstructed electron diffraction pattern was confirmed to be qualitatively equal to that of the selected-area electron diffraction pattern, though the degree of the equivalency between these patterns reduces at the high frequency region and the reproducibility of the intensity degrades when the number of images used in the image processing was decreased. By selecting areas in a reconstructed exit wave field, some electron diffraction patterns were obtained from the nano-areas without the influence of spherical aberration.     

An 80-Gb/s optoelectronic delayed flip-flop IC using resonanttunneling diodes and uni-traveling-carrier photodiode

This paper describes an 80-Gb/s optoelectronic delayed flip-flop (D-FF) IC that uses resonant tunneling diodes (RTDs) and a uni-traveling-carrier photodiode (UTC-PD). A circuit design that considers the AC currents passing through RTDs and UTC-PD is key to boosting circuit operation speed. A monolithically fabricated IC operated at 80 Gb/s with a low power dissipation of 7.68 mW. The operation speed of 80 Gb/s is the highest among all reported flip-flops. To clarify the maximum operation speed, we analyze the factors limiting circuit speed. Although the bandwidth of UTC-PD limits the maximum speed of operation to 80 Gb/s at present, the circuit has the potential to offer 100-Gb/s-class operation     

Generation control circuit for photovoltaic modules

Photovoltaic modules must generally be connected in series in order to produce the voltage required to efficiently drive an inverter. However, if even a very small part of photovoltaic module (PV module) is prevented from receiving light, the generation power of the PV module is decreased disproportionately. This greater than expected decrease occurs because PV modules which do not receive adequate light cannot operate on the normal operating point, but rather operate as loads. As a result, the total power from the PV modules is decreased if even only a small part of the PV modules are shaded. In the present paper, a novel circuit, referred to as the generation control circuit (GCC), which enables maximum power to be obtained from all of the PV modules even if some of the modules are prevented from receiving light. The proposed circuit enables the individual PV modules to operate effectively at the maximum power point tracking, irrespective of the series connected PV module system. In addition, the total generated power is shown experimentally to increase for the experimental set-up used in the present study     

Nitric oxide decomposition in air by using nonthermal plasmaprocessing with additives and catalyst

Catalyst (copper-coated zeolite catalyst, i.e., Cu-ZSM-5) was used to enhance NO_x removal plasma chemical reactions. Two kinds of hydrocarbons (2-propane-1-ol, 2-propanol) were added to the synthesized flue gas before the nonthermal plasma process, and their effects on NO_x removal characteristics were investigated. Enhancement effects of NO_x removal by the nonthermal plasma process with hydrocarbons as the additives were confirmed. Usually, the catalyst's working temperature is much higher than the room temperature. A catalytic reactor was installed after the plasma reactor. Catalytic effects on NO_x removal characteristics disappeared when the synthesized flue gas temperature was increased (~250°C). When the synthesized flue gas temperature was at room temperature, about 90% NO _x removal efficiency was realized with a combination of hydrocarbons, the catalytic reactor, and the pulsed discharge plasma     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors