基于多核DSP的星载SAR干扰信号生成算法优化

针对星载合成孔径雷达(SAR)的特点,提出了一种基于多核数字信号处理器(DSP)的欺骗式干扰实时产生算法优化方法,该方法使用了哈希查找表、动态/静态计算分离等技术,并针对DSP芯片硬件架构进行算法优化,达到了实时生成星载SAR欺骗式干扰信号的目的,为星载SAR 欺骗式干扰信号实时产生提供了技术手段,并为其他基于DSP的数字信号处理算法提供了一种可行的优化思路。文中针对算法设计与工程实现中影响实时性的关键问题进行分析,并针对典型合成孔径雷达进行验证,证明了该方法的有效性与实时性。     

CONDITIONAL FACTORIZATION BASED ON LATTICE THEORY FOR 〈K,1〉-INTEGERS

In this paper, the integer N = p^kq is called a 〈k, 1〉-integer, if p and q are odd primes with almost the same size and k is a positive integer. Such integers were previously proposed for various cryptographic applications. The conditional factorization based on lattice theory for n-bit 〈k, 1〉-integers is considered, and there is an algorithm in time polynomial in n to factor these integers if the least significant ｜（2k - 1）n/（3k-1）（k＋1）｜ bits of p are given.     

Performances comparison of pulse-pair and 2-step prediction algorithms for the doppler spectrum estimation

In this work we use real data provided by terminal pulse Doppler radar (WSR-88D) echoes to estimate the windshear hazards disastrous for the aircraft takeoffs and landings. Briefly two different methods are used to estimate the received Doppler moments. The second central moment which is the variance of the wind speed is called width or shear. A first method is in the time domain and also called pulse-pair, while the second is in the frequency domain. The main aim of this study is a performances comparison of results provided by the two mentioned methods and assumes that the power spectrums of the received signals are approached with the Gaussian shape.     

In-situ cleaning and passivation of oxidized Cu surfaces by alkanethiols and its application to wire bonding

The treatment of oxidized Cu surfaces using an alkanethiol as a reducing agent has been investigated. Exposure to a dilute solution of 1-decanethiol resulted in the complete removal and/or conversion of CuO and subsequent formation of a passivating thiolate film, a so-called self-assembled monolayer (SAM), on the underlying Cu/Cu₂O surface as evidenced by x-ray photoelectron spectroscopy (XPS) analysis. Morphological changes, monitored by scanning electron microscopy (SEM) and atomic force microscopy (AFM), revealed transformation of the rough, porous CuO layer into a comparatively smooth Cu/Cu₂O surface. Experiments performed on integrated circuit back-end-of-line (BEOL) die structures, comprising Cu/SiO₂ bond pads used as substrates for Cu wire bonding, demonstrate the potential application of a thiol-based in-situ cleaning-passivation procedure in microelectronics.     

New two CFOA-based sinusoidal RC oscillators with buffered outlet

Using a unified representation for a class of buffered-outlet two current-feedback operational amplifier (CFOAs)-based sinusoidal oscillators, new circuits of this type can be systematically discovered. A catalogue of four circuit structures, each structure realizing nine oscillator circuits, is presented. Moreover, using the RC:CR transformation, additional nine oscillator circuits can be obtained from each structure. While each circuit requires five passive elements, some of the circuits enjoy one or more of the following attractive features: use of grounded capacitors, feasibility of absorbing the parasitic components of the CFOAs and orthogonal tuning of the frequency and the startup condition of oscillation.     

Collaborative and Cognitive Network Platforms: Vision and Research Challenges

In this paper, we present a visionary concept referred to as Collaborative and Cognitive Network Platforms (CCNPs) as a future-proof solution for creating a dependable, self-organizing and self-managing communication substrate for effective ICT solutions to societal problems. CCNP creates a cooperative communication platform to support critical services across a range of business sectors. CCNP is based on the personal network (PN) technology which is an inherently cooperative environment prototyped in the Dutch Freeband PNP2008 and the European Union IST MAGNET projects. In CCNP, the cognitive control plane strives to exploit the resources to better satisfy the requirements of networked applications. CCNP facilitates collaboration inherently. Through cognition in the cognitive control plane, CCNP becomes a self-managed substrate. The self-managed substrate, in this paper, is defined as cognitive and collaborative middleware on which future applications run without user intervention. Endemic sensor networks may be incorporated into the CCNP concept to feed its cognitive control plane. In this paper, we present the CCNP concept and discuss the research challenges related to collaboration and cognition.     

Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition

Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from super-linear increases in computational time with increasing data size and number of signals being processed (data dimension). Certain principal machine-learning algorithms are commonly found embedded in larger detection, estimation, or classification operations. Three such principal algorithms are the Parzen window-based, non-parametric estimation of Probability Density Functions (PDFs), K-means clustering and correlation. Because they form an integral part of numerous machine-learning applications, fast and efficient execution of these algorithms is extremely desirable. FPGA-based reconfigurable computing (RC) has been successfully used to accelerate computationally intensive problems in a wide variety of scientific domains to achieve speedup over traditional software implementations. However, this potential benefit is quite often not fully realized because creating efficient FPGA designs is generally carried out in a laborious, case-specific manner requiring a great amount of redundant time and effort. In this paper, an approach using pattern-based decomposition for algorithm acceleration on FPGAs is proposed that offers significant increases in productivity via design reusability. Using this approach, we design, analyze, and implement a multi-dimensional PDF estimation algorithm using Gaussian kernels on FPGAs. First, the algorithm’s amenability to a hardware paradigm and expected speedups are predicted. After implementation, actual speedup and performance metrics are compared to the predictions, showing speedup on the order of 20× over a 3.2 GHz processor. Multi-core architectures are developed to further improve performance by scaling the design. Portability of the hardware design across multiple FPGA platforms is also analyzed. After implementing the PDF algorithm, the value of pattern-based decomposition to support reuse is demonstrated by rapid development of the K-means and correlation algorithms.     

Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems

As an attractive technique for peak-to-average power ratio (PAPR) reduction in orthogonal frequency division multiplexing (OFDM) systems, time domain interleaved partitioning partial transmit sequence (TD-IP-PTS) scheme uses circular convolution property of discrete Fourier transforms (DFT) so as to need only one inverse fast Fourier transform (IFFT) operation. However, the search and combination of phase factors still need higher computational complexity. In order to improve the problem, this paper detailedly analyzes the independence of phase factor vectors and optimizes the phase factor vectors in TD-IP-PTS. Furthermore, we find the characteristic of combination of phase factors and propose three methods respectively based on storage-unit, pipeline and select-path to implement the combination of phase factors in TD-IP-PTS. The simulation results show that TD-IP-PTS using independent and effective phase factor vectors has better PAPR performance and lower complexity than traditional IP-PTS. Moreover, among three proposed methods for combination of phase factors, the method based on select-path requires the least registers and delay time. This method is the most promising in practical applications.     

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K ×2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.