A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Untersuchung der Verteilung und Intensität filamentierter Barrierenplasmen für die Behandlung von Oberflächen

The application of barrier discharges at atmospheric pressure in air expands on the market of plasma technology, because it is an ecological and cost‐effective alternative to other processes of surface treatment. These plasmas usually consist of a multitude of spatially and temporally localized filaments, whose distribution should be as even as possible for homogeneous treatment. This holds especially for the plasma treatment of sensitive goods such as wool or other textiles. In equipment for continuous pass of material the barrier arrangements often consist of a system cylinder – cylinder or cylinder – plane, whereby the gap width changes locally. Space distribution and intensity of filaments has been investigated by means of short‐time photography and spatially resolved measurement of current distribution and energy distribution derived from it. The local dependency found can be explained by means of a capacitive equivalent circuit.     

Oxidative degradation of polyamide reverse osmosis membranes: Studies of molecular model compounds and selected membranes

Selected aromatic amides were used to model the chemical reactivity of aromatic polyamides found in thin‐film composite reverse osmosis (RO) membranes. Chlorination and possible amide bond cleavage of aromatic amides upon exposure to aqueous chlorine, which can lead to membrane failure, were investigated. Correlations are made of the available chlorine concentration, pH, and exposure time with chemical changes in the model compounds. From the observed reactivity trends, insights are obtained into the mechanism of RO membrane performance loss upon chlorine exposure. Two chemical pathways for degradation are shown, one at constant pH and another that is pH‐history dependent. An alternative strategy is presented for the design of chlorine‐resistant RO membranes, and an initial performance study of RO membranes incorporating this strategy is reported. © 2003 Wiley Periodicals, Inc. J Appl Polym Sci 90: 1173–1184, 2003     

Robust vector control of induction motors using full-order observer in consideration of core loss

This paper proposes a method for designing a robust full-order observer for vector-controlled induction motors taking core loss into account. Although conventional research focuses on parameter identification, global stability of the identification remains questionable. Therefore, robustness against some parameters is required. This paper describes the design of a robust full-order observer which takes core loss into account, using both the gain-scheduled H/sub /spl infin// control and the linear matrix inequality technique. This design always results in a stable controller. The robustness of the proposed method against variations of resistances is evaluated by experiments.     

Assessing stem cell research productivity

Honour Index (HoI), a method to evaluate research performance within different research fields, was derived from the impact factor (IF). It can be used to rate and compare different categories of journals. HoI was used in this study to determine the scientific productivity of stem cell research in the Asian Four Dragons (Hong Kong, Singapore, South Korea and Taiwan) from 1981 to 2001. The methodology applied in this study represents a synthesis of universal indicator studies and bibliometric analyses of subfields at the micro-level. We discuss several comparisons, and conclude the developmental trend in stem cell research for two decades. This revised version was published online in August 2006 with corrections to the Cover Date.     

Micro-prober for wafer-level low-noise measurements in MOS devices

Low-frequency noise measurements represent an interesting investigation technique for the characterization of the quality and reliability of microelectronic materials and devices. Performing meaningful noise measurements at low and very low (f<1 Hz) frequencies, however, may be quite challenging, particularly because of the many sources of interference that superimpose on the noise signal. For this reason, packaged samples are preferred because they allow accurate shielding from the external environment, and because keeping the sample in close proximity to the low-noise biasing system and amplifier reduces microphonic and electromagnetic disturbances. Notwithstanding this, the possibility of performing low-frequency noise measurements at wafer level would be quite interesting, both because of the ease of obtaining wafer-level samples from industries with respect to packaged samples, and because this would avoid possible packaging-process induced device degradation. The purpose of this work is to demonstrate that it is, in fact, possible to design and build a dedicated probe system for performing high-sensitivity, low-frequency noise measurements on metal-oxide-semiconductor devices at wafer level.     

A comparison of transformation methods for evaluating two‐dimensional weakly singular integrals

Accurate numerical evaluation of integrals arising in the boundary element method is fundamental to achieving useful results via this solution technique. In this paper, a number of techniques are considered to evaluate the weakly singular integrals which arise in the solution of Laplace's equation in three dimensions and Poisson's equation in two dimensions. Both are two‐dimensional weakly singular integrals and are evaluated using (in a product fashion) methods which have recently been used for evaluating one‐dimensional weakly singular integrals arising in the boundary element method. The methods used are based on various polynomial transformations of conventional Gaussian quadrature points where the transformation polynomial has zero Jacobian at the singular point. Methods which split the region of integration into sub‐regions are considered as well as non‐splitting methods. In particular, the newly introduced and highly accurate generalized composite subtraction of singularity and non‐linear transformation approach (GSSNT) is applied to various two‐dimensional weakly singular integrals. A study of the different methods reveals complex relationships between transformation orders, position of the singular point, integration kernel and basis function. It is concluded that the GSSNT method gives the best overall results for the two‐dimensional weakly singular integrals studied. Copyright © 2002 John Wiley & Sons, Ltd.     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.