Design for concurrent error detection and testability instorage/logic arrays

Storage/Logic Arrays (SLA's) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and multiple levels of logic. A means of designing SLA's for ease of testability and concurrent error detection (CED) is provided in this paper. Test sets for static and dynamic CMOS circuits are described. Fault and error coverage is presented and performance and area costs are analyzed for example circuits. In addition, a means of implementing dynamic CMOS SLA's is presented and shown superior to previous NMOS, static CMOS, and dynamic CMOS approaches based upon power consumption and simplicity of design     

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportionalself-timing generator

This 512 Kw×8 b×3 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator and a 0.4-μm BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Newly developed circuit technologies include: 1) a zig-zag double word-line scheme, 2) a centered bit-line load layout scheme, and 3) a phase-locked-loop (PLL) with a multistage-tapped ring oscillator which generates a clock cycle proportional pulse (CCPP) and a clock edge lookahead pulse (CELP)     

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 μm BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55°C     

A video DSP with a macroblock-level-pipeline and a SIMD typevector-pipeline architecture for MPEG2 CODEC

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V     

Motion control with permanent-magnet AC machines

Motion control techniques have been developed to exploit the high efficiency and extremely fast dynamic response capabilities of permanent-magnet AC (PMAC) machines. Control techniques are reviewed separately for the two major classes of PMAC machines referred to as trapezoidal (i.e., brushless DC) and sinusoidal machines. While trapezoidal PMAC machine drives are distinguished by their controls simplicity and minimal sensor requirements, sinusoidal PMAC machine drives offer opportunities for extremely smooth torque production and extended high-speed operating ranges. Advanced PMAC machine control topics including sensor elimination techniques and robust servocontrol algorithms are reviewed, concluding with a discussion of PMAC machine drive application trends     

Latest advances in camcorder technology

Camcorders have been developed to be compact with high performance. Latest advancement of key technologies and devices such as digital signal processing LSI, six-layer printed circuit board with micro chips, high-speed power lens with linear motor, 103 K pixels 0.7-in LCD electronic viewfinder, and high-energy Li-ion battery are described. High-band format is also explained     

Marcian E. Hoff Jr

The author presents a profile of Marcian E.(Ted) Hoff, the architect of the first commercial microprocessor and the single chip coder/decoder (codec). Hoff has turned a lifelong interest in collecting electronic components into a career as high-tech detective, helping patent attorneys defend their cases. In his crowded home workshop, Hoff has over 15,000 ICs inventoried and filed, along with various PCs, oscilloscopes and other instruments     

Comment on raindrop size distribution model

The parameter set for the exponential raindrop size distribution model presented by Yeo, Kooi and Leong (see ibid. vol.41, P.709, 1993) was derived using a data set measured in Singapore. A limitation to the model is that it is accurate only for small rain rate or when the rain medium consists predominantly of small droplets with diameter D is < λ/π . A new parameter set that enables accurate computation of rain attenuation for droplets with diameter D = λ/π has since been derived using the same data set. This new parameter set has been proven to be more accurate in the computation of rain attenuation     

Mutual impedance between skewed patch antennas

This paper considers the mutual impedance between skewed rectangular microstrip patch antennas as a function of the skew angle. The analysis is done using the exact Green's function for the patch and the method of moments to solve for the field. The theoretical results obtained are compared with published experimental results     

DCS的评价与选择

本文综述了ＤＣＳ（集散控制系统）三代产品的总体水平评价，介绍了ＤＣＳ的总体性能、评价指标和它的选择准则。