三种可视化技术在驱油剂评价中的适应性

针对可视化技术在驱油剂评价中适用范围不明确的问题,对比了可视化微观物理驱替模型、计算机X线断层扫描(CT)和核磁共振成像(MRI)三种可视化技术的原理与功能,分析了它们在驱油剂评价中的应用范围与存在的问题。可视化微观物理驱替模型和CT适用于驱油剂驱油机理的研究,前者侧重于微观,后者侧重于宏观;CT和MRI适用于驱油剂驱油性能的评价,前者侧重于轻质油体系下剩余油饱和度的沿程分布,后者侧重于稀油体系下剩余油在不同孔径孔隙内的分布。     

电力线载波通讯在热网温度监测系统中的应用

采用智能温度传感器DS18B20、热电偶及电力线载波应用于热网温度监测系统。建立了系统总体方案和拓扑结构图、选择了温度传感器,及相应的软硬件系统。实际运行表明,该系统抗干扰能力强,信号传输距离远,能够满足监测系统的要求。     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

Optical neurochip with learning capability

A dynamic optical neurochip with variable synaptic interconnection capability has been reported. A novel type of photodetector called a variable sensitivity photodetector has been developed for the synaptic interconnection of neural networks. It utilizes a metal-semiconductor-metal structure whose quantum efficiency can be modulated by an applied bias voltage. The fabricated dynamic optical neurochip consists of an 8×8 variable sensitivity photodetector (VSPD) array and an 8 line-shaped LED array. It is shown that this device is suitable for learning in neural networks. The application to pattern classification is demonstrated     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

Comparison of measured value and calculated value of multiplestability in forced-flow cooled superconductors

The multiple stability observed exclusively in forced-flow cooled superconductors is numerically calculated, and the result is quantitatively compared with the value measured by J.W. Lue et al. (1980). The calculated and measured values agreed well in certain cases, and did not in others. Based on this comparison, the effects of the transient heat transfer coefficient and ohmic heat generation on the quantitative prediction of stability are discussed. From this comparison, it is learned that a precise understanding of the transient heat transfer coefficient is essential for reliable predictions, and also that the ordinary evaluation method of ohmic heat generation, which considers the flux-flow resistance, tends to overevaluate the situation     

A novel on-chip electrostatic discharge (ESD) protection withcommon discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure     

A 0.9-V microcontroller for portable applications

A 0.9-1.6-V, 1-MHz, 8-b microcontroller based on the 68HC08 architecture is presented. In addition to standard digital microcontroller functions, the chip features RAM, ROM, phase-locked loop (PLL) clock synthesis, and liquid crystal displays (LCD) drive capabilities operating from the voltage supply range of a single AA or AAA battery. The design used a library of CMOS microcontroller building blocks, converted into a low-voltage technology using unilateral transistors. The design approach was to optimize the conversion strategy for each functional block and to provide new designs when the conversion was insufficient. The chip exceeded specifications with blocks showing full functionality down to 0.7 V     

Designing better adaptive sampling algorithms for ECG Holtersystems

Let Ψ be any adaptive sampling algorithm that can run in real time on a tapeless multichannel electrocardiogram (ECG) Holter system. Simple methods which can significantly improve Ψ's fidelity are described and their results are compared in this paper. It is shown that by adding some simple tests to Ψ, the signals reconstructed by Ψ can be improved as much as 5.45 dB. It is also shown that under the same data rate, a good data compressor with slowly sampled input ECG is preferable to a bad data compressor with highly sampled input ECG