A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm² die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power     

Different Directions of Switching of Chromium Oxide Thin Films

We have investigated the switching behavior of as-deposited CrO _x and post-annealed CrO _y films by use of a variety of electrodes (top electrode Ag, Ti; bottom electrode Pt, fluorine tin oxide (FTO)). Resistance switching is highly dependent on electrode material and post-annealing treatment. Among Pt devices, I–V hysteresis was observed for the Ag/CrO _x /Pt device only; no resistance switching was observed for Ag/CrO _y /Pt, Ti/CrO _x /Pt, and Ti/CrO _y /Pt devices. Among FTO devices, I–V hysteresis was observed for the Ag/CrO _x /FTO device whereas I–V hysteresis with the opposite switching direction was observed for Ag/CrO _y /FTO, Ti/CrO _x /FTO, and Ti/CrO _y /FTO devices. The direction of switching depends not only on electrode material but also on post-annealing treatment, which affects the density of grain boundaries. Thus, the density of grain boundaries determines the type of charge carrier involved in the switching process. For as-deposited CrO _x films with a high density of grain boundaries Ag filament paths mediated by electrochemical redox reaction were observed, irrespective of bottom electrode material (Pt or FTO). Post-annealed CrO _y films with a low density of grain boundaries suppressed electrochemical redox reaction in the Ag/CrO _y /Pt device but promoted short-range movement of O^2? ions through the bottom interface, resulting in resistance switching in the Ag/CrO _y /FTO device. Electrochemical redox reaction-controlled resistance switching occurred solely in oxides with a high density of grain boundaries or dislocations.     

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length = 90 nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.     

Highly stable fiber Bragg gratings written in hydrogen-loaded fiber

We demonstrated that the thermal stability of fiber Bragg gratings written in hydrogen-loaded standard fibers can be significantly enhanced by preirradiating the fiber with UV beam before writing gratings. Our experimental result shows that these gratings maintained more than 60% of their initial index modulation after 10 hours at 605/spl deg/C.     

Off-state drain breakdown mechanisms of VDMOS with anti-JFET implantation

Efficiency, reliability, and cost are the important design considerations of a vertical double diffused MOSFET (VDMOS) because of its high-voltage applications in consumer electronics. To minimize the cost, the devices were normally fabricated on an epitaxial layer which was grown on a highly-doped substrate. Meanwhile, it was proposed that the efficiency of a VDMOS can be enhanced by conducting an anti-JFET implant to reduce the “ON” resistance of the transistor. This paper reports the effects of anti-JFET implant on the reliability and the blocking capability of the VDMOS. Experimental results show that the anti-JFET implant can reduce the ON resistance by suppressing the channel depletion due to the parasitic JFET and enhance the breakdown voltage by moving the high-field region to the surface channel region. However, it deteriorates the device reliability greatly because the oxide quality was deteriorated and the hot holes generated in the surface high-field region could be easily injected into the gate oxide and hence caused larger subthreshold conduction and drain breakdown at lower voltage.     

A Semi-Theoretical Fluorescent Lamp Model for Time-Domain Transient and Steady-State Simulations

Low-pressure discharge lamps obey a set of physical laws that are different from those of high-pressure discharge lamps. In this paper, these differences are addressed. Based on a recently developed HID lamp model frame, a semi-theoretical fluorescent lamp model that can be determined by genetic algorithms and simple electrical measurements is presented. This model does not require any lamp data from lamp manufacturers. Its parameters can be determined from electrical voltage and current measurements of the lamps under AC operation at mains frequency. With the same set of parameters, the model can predict the lamp terminal characteristics accurately under low, medium and high frequency operations. Good simulation results were achieved when the lamp power was reduced to 60% of rated power and when the lamp was operated under step-up and step-down transient processes. Simulation results for different sizes of tubular and compact fluorescent lamps agree well with their experimental results. Particularly, the differences between simulation results and experimental results under rated power are less than 10%. Hence, the proposed model shows a good degree of accuracy: 1) for different types of fluorescent lamps; 2) at different operating frequencies; 3) under different dimming levels; and 4) during step-up and step-down transient processes.     

IPTV的关键广播构建模块

电信运营商和电视运营商在为消费者提供视频内容服务上不断展开竞争。然而，与电视运营商相比，大部分电信运营商的基础设施还不具备传输高质量视频所需的带宽。因此，在内容分配上，电信运营商没有使用正交振幅调制（QAM）和MPEG2视频编码等数字调制技术，而是采用了互联网协议（IP）网络，利用MPEG4-Part10（也称为H．264-AVC）等新的编码方案来为消费者提供视频内容。     

Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.