Writing current reduction and total set resistance analysis in PRAM

We evaluated the limit of scaling bottom electrode contact (BEC) heater size and high resistivity heater to reduce writing current. It was found that the resistivity of heater should be increased for reducing writing current below the heater size of about 50 nm without any undesirable increase of resistance of the crystalline state (SET state, Rset). It was shown in the numerical simulations that the dissipated heat loss through BEC during melting GST was decreased in the increase of resistivity of heater. In addition, we analyzed the resistance components contributing to the total set resistance. It was observed that the undesired sharp increase of Rset as the BEC size decreases below 50 nm was attributed to the resistance component of GST–BEC interface. In the case of high resistivity heater, the contributions of both incomplete crystallization and heater itself were enhanced.     

防空兵火控雷达综合抗干扰能力评估

对防空兵火控雷达面临的主要干扰及其所采取的主要抗干扰措施进行了分析,建立了防空兵火控雷达综合抗干扰能力评估模型,并对防空兵火控雷达综合抗干扰能力进行了评估。     

0.13μm射频MOS场效应晶体管特性及模拟

采用0.13μm CMOS射频和混合信号工艺进行了射频nMOS场效应晶体管版图的优化设计和芯片制作.对制作的射频nMOS器件进行了直流特性和S参数测试,测试结果表明射频nMOS管的特征频率fT达到了93GHz,fmax超过了90GHz.采用小信号等效电路模型对该nMOS管的交流特性进行了模拟.在100MHz到30GHz频率范围内得到了与测试结果相吻合的仿真结果.     

Performance Analysis of Incremental Amplify-and-Forward Relaying Protocols with Nth Best Partial Relay Selection Under Interference Constraint

In this paper, we investigate two incremental amplify-and-forward relaying protocols in cognitive underlay networks. In the proposed protocols, whenever the secondary destination cannot receive the secondary source’s signal successfully, it requests a retransmission from one of M secondary relays. In the first protocol, we assume that a secondary relay with the Nth best channel gain to the secondary source is used to forward the received signal to the secondary destination. In the second protocol, relying on the quality of channels between the secondary relay and secondary destination and between the secondary relay and primary user, the Nth best relay is chosen for the retransmission. We derive exact closed-form expressions of the outage probability and average number of time slots for both protocols over Rayleigh fading channel. Finally, these mathematical expressions are then verified by Monte Carlo simulations.     

基于局部图划分的多相活动轮廓图像分割模型

几何活动轮廓模型是图像分割领域的强有力工具。最近,一种基于成对相似性的图划分活动轮廓(GPAC)模型被提出,并有效应用于均质图像分割。但是,该模型的连接权函数仅与图像光谱相关,使得模型在低对比度模糊图像的应用存在较大局限,同时,成对相似性的计算量大,模型的数值实现效率不甚理想。针对这些问题,该文引入测地核函数定义连接权函数,结合多相水平集,提出了基于局部图划分的多相活动轮廓图像分割模型。自然图像的实验结果证明了该模型的有效性。     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Pixel‐Structured Scintillator with Polymeric Microstructures for X‐Ray Image Sensors

We introduce a pixel‐structured scintillator realized on a flexible polymeric substrate and demonstrate its feasibility as an X‐ray converter when it is coupled to photosensitive elements. The sample was prepared by filling Gd₂O₂S:Tb scintillation material into a square‐pore‐shape cavity array fabricated with polyethylene. For comparison, a sample with the conventional continuous geometry was also prepared. Although the pixelated geometry showed X‐ray sensitivity of about 58% compared with the conventional geometry, the resolving power was improved by about 70% above a spatial frequency of 3 mm^?1. The spatial frequency at 10% of the modulation‐transfer function was about 6 mm^?1.     

MOS结构电容高频C-V特性的应用

CMOS工艺的发展要求栅介质层厚度不断减薄,随着栅极漏电流的不断增大使用准静态的方法测量器件特性不稳定。根据这一情况,提出用高频电容电压(C-V)来评价深亚微米和超深亚微米器件工艺。通过高频C-V法结合MOS相关理论可以得到介质层的厚度、最大耗尽层宽度、阈值电压、平带电压等参数以及栅介质层中各种电荷密度的分布,用以评价栅介质层和衬底的界面特性。文章提出通过电导对测量结果进行修正,使其能够适用更小尺寸器件的要求,使高频C-V法能够在不同的工艺下得到广泛的应用。