小波分析在流化床两相流信号处理中的应用

本文根据流化床锅炉内气泡相与密相中颗粒浓度信号的频谱特性的差异,采用小波方法确定两相交替出现的时刻,提取其中气泡相颗粒浓度信号,应用局部互相关方法求取床内气泡运动参数,并给出了气泡运动参数的统计规律．结果表明,该方法是有效的．     

接入网用新型配线光缆和引入光缆

简要地叙述了接入网用新型配线和引入光缆的结构、特点及性能     

Delay guarantee of virtual clock server

In a packet switching network, each communication channel is statistically shared among many traffic flows that belong to different end-to-end sessions. We present and prove a delay guarantee for the virtual clock service discipline (inspired by time division multiplexing). The guarantee has several desirable properties, including the following firewall property: the guarantee to a flow is unaffected by the behavior of other flows sharing the same server. There is no assumption that sources are flow controlled or well behaved. We first introduce and define the concept of an active flow. The delay guarantee is then formally stated as a theorem. We show how to obtain delay bounds from the delay guarantee of a single server for different specifications     

Code Compression for VLIW Embedded Systems Using a Self-Generating Table

We propose a new class of methods for VLIW code compression using variable-sized branch blocks with self-generating tables. Code compression traditionally works on fixed-sized blocks with its efficiency limited by their small size. A branch block, a series of instructions between two consecutive possible branch targets, provides larger blocks for code compression. We compare three methods for compressing branch blocks: table-based, Lempel-Ziv-Welch (LZW)-based and selective code compression. Our approaches are fully adaptive and generate the coding table on-the-fly during compression and decompression. When encountering a branch target, the coding table is cleared to ensure correctness. Decompression requires a simple table lookup and updates the coding table when necessary. When decoding sequentially, the table-based method produces 4 bytes per iteration while the LZW-based methods provide 8 bytes peak and 1.82 bytes average decompression bandwidth. Compared to Huffman's 1 byte and variable-to-fixed (V2F)'s 13-bit peak performance, our methods have higher decoding bandwidth and a comparable compression ratio. Parallel decompression could also be applied to our methods, which is more suitable for VLIW architectures.     

Spacer visibility problem in field emission displays due to surface contamination

Spacer visibility is a critical issue in field emission displays (FEDs). Many reasons can lead to visible spacers, such as charging due to secondary electron emission under electron bombardment. In this paper, we will present results on spacer visibility due to chemical contamination on the spacer surface. We have identified Na contamination as the cause for the white spacer problem observed in the early developing stage of FED. The diffusion of Na from spacers to its adjacent cathode area during field emission operation caused higher field emission current from those field emitters. We believe the higher emission is due to the temporary gettering effect from the Na species, which cleaned the local field emitters. We have also found the existence of Pb on the spacer surface could create the dark spacer problem. To avoid any spacer visibility problem, the spacer surface must be kept clean. Any post clean procedure used to clean the surface should not leave any trace of elements such as Na, or Pb.     

Robust common visual pattern discovery using graph matching

Discovering common visual patterns (CVPs) between two images is a difficult and time-consuming task, due to the photometric and geometric transformations. The state-of-the-art methods for CVPs discovery are either computationally expensive or have complicated constraints. In this paper, we formulate CVPs discovery as a graph matching problem, depending on pairwise geometric compatibility between feature correspondences. To efficiently find all CVPs, we propose a novel framework which consists of three components: Preliminary Initialization Optimization (PIO), Guided Expansion (GE) and Post Agglomerative Combination (PAC). PIO gets the initial CVPs and reduces the search space of CVPs discovery, based on the internal homogeneity of CVPs. Then, GE anchors on the initializations and gradually explores them, to find more and more correct correspondences. Finally, to reduce false and miss detection, PAC refines the discovery result in an agglomerative way. Experiments and applications conducted on benchmark datasets demonstrate the effectiveness and efficiency of our method.     

Wideband Extended Range-Doppler Imaging and Waveform Design in the Presence of Clutter and Noise

This paper presents a group-theoretic approach to address the wideband extended range-Doppler target imaging and design of clutter rejecting waveforms. An exact imaging method based on the inverse Fourier transform of the affine group is presented. A Wiener filter is designed in the affine group Fourier transform domain to minimize wideband clutter range-Doppler reflectivity. The Wiener filter is then used to form an operator to precondition transmitted waveforms to reject clutter. Alternatively, the imaging and clutter rejection methods are equivalently re-expressed to perform clutter suppression upon reception. These methods are coupled with noise suppression upon reception. Numerical simulations are performed to demonstrate the performance of the proposed approach. Our study shows that the framework introduced in this paper can address the joint design of receive and transmit processing, design of clutter rejecting waveforms, suppression of noise, and reduction of computational complexity in receive processing     

发射机的射频搭接技术及有效性分析

论文介绍了搭接及搭接的作用,阐述了搭接类型与搭接技术的一般原则,结合实例分析了发射机系统的射频搭接技术有效性及射频搭接不良对发射机稳定运行造成的不良影响。     

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V _dd assignment, multiple V _th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.