LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.     

A Systematic Approach to Achieving High Performance Hybrid Lighting Phosphors with Excellent Thermal‐ and Photostability

The authors have designed and synthesized a family of high‐performance inorganic–organic hybrid phosphor materials composed of extended and robust networks of one, two, and three dimensions. Following a bottom‐up solution‐based synthetic approach, these structures are constructed by connecting highly emissive Cu₄I₄ cubic clusters via carefully selected ligands that form strong Cu? N bonds. They emit intensive yellow‐orange light with high luminescence quantum efficiency, coupled with large Stokes shift, which greatly reduces self‐absorption. They also demonstrate exceptionally high framework‐ and photostability, comparable to those of commercial phosphors. The high stabilities are the result of significantly enhanced Cu? N bonds, as confirmed by the density functional theory (DFT) binding energy and electron density calculations. Possible emission mechanisms are analyzed based on the results of theoretical calculations and optical experiments. Two‐component white phosphors obtained by blending blue and yellow emitters reach an internal quantum yield as high as 82% and correlated color temperature as low as 2534 K. The performance level of this subfamily exceeds all other types of Cu–I based hybrid systems. The combined advantages make them excellent candidates as alternative rare‐earth element‐free phosphors for possible use in energy‐efficient lighting devices.     

Simulation of single phase non-Newtonian flow characteristics of heavy crude oil through horizontal pipelines

The effect of diameter, velocity, and temperature on flow properties of heavy crude oil in three horizontal pipelines using computational fluid dynamics (CFD) was studied. The flow characteristics were simulated by using CFD software, ANSYS Fluent 6.2. The mesh geometry of the pipelines having inner diameter of 1, 1.5, and 2 inch were created by using Gambit 2.4.6. From grid independent study, 221, 365 mesh sizes were selected for simulation. The CFD ANSYS Fluent 6.2 Solver predicted the flow phenomena, pressure, pressure drop, wall shear stress, shear strain rate, and friction factor. A good agreement between experimental and CFD simulated values was obtained.     

Design of testable sequential circuits by repositioning flip-flops

This paper presents a technique to enhance the testability of sequential circuits by repositioning flip-flops. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan flip-flops to break all cycles (except self-loops) as compared to the original circuit. Our technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit graph to minimize the number of flip-flops in the SCCs. A circuit graph has a vertex for every gate, primary input and primary output. If gatea has a fanout to gateb, then the circuit graph has an arc from vertexa to vertexb. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique in reducing the number of partial scan flip-flops.     

Estimation of parameters of a model of a complex repairable system

This paper deals with estimation of parameters of a model of a complex repairable system with 3ne unit on operation and the remaining (N − 1) units as inactive standbys and having a repair facility. Various operating characteristics, namely, reliability, availability, mean time to failure of the system, s-expected numbers of repairs in (0, t], s-expected numbers of failures of the system in (0, t] are estimated under two censoring schemes namely, the type-I censoring and type-II censoring schemes.     

Modeling of transient natural convection heat transfer in electric ovens

Prediction of transient natural convection heat transfer in vented enclosures has multiple applications such as understanding of cooking environment in ovens and heat sink performance in electronic packaging industry. The thermal field within an oven has significant impact on quality of cooked food and reliable predictions are important for robust design and performance evaluation of an oven. The CFD modeling of electric oven involves three-dimensional, unsteady, natural convective flow-thermal field coupled with radiative heat transfer. However, numerical solution of natural convection in enclosures with openings at top and bottom (ovens) can often lead to non-physical solutions such as reverse flow at the top vent, partly a function of initialization and sometimes dependent on boundary conditions. In this paper, development of a physics based robust CFD methodology is discussed. This model has been developed with rigorous experimental support and transient validation of this model with experiments show less than 3% discrepancy for a bake cycle. There is greater challenge in simulating a broil cycle, where the fluid inside the cavity is stably stratified and is also highlighted. A comparative analyses of bake and broil cycle thermal fields inside the oven are also presented.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

扭摆式微硅隧道加速度传感器

本文介绍了扭摆式隧道加速度传感器的结构、工作原理、简化的力学模型,设计了版图、工艺流程及关键工艺,并制备出样品,最后给出测试电路和结果。     

Transactions Letters - Outage Capacity and Optimal Power Allocation for Multiple Time-Scale Parallel Fading Channels

In this paper, we address the optimal power allocation problem for minimizing capacity outage probability in multiple time-scale parallel fading channels. Extending ideas from the work of Dey and Evans (2005), we derive the optimal power allocation scheme for parallel fading channels with fast Rayleigh fading, as a function of the slow fading gains. Numerical results are presented to demonstrate the outage performance of this scheme for lognormal slow fading on two parallel channels.     

Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field

The growth of a high quality, step-graded lattice-relaxed SiGe buffer layer on a Si(100) substrate is investigated. p-MOSFETs were fabricated on strained-Si grown on top of the above layer. Carrier confinement at the type-II strained-Si/SiGe buffer interface is observed clearly from the device transconductance and C-V measurements. At high vertical field, compared to bulk silicon, the channel mobility of the strained-Si device with x=0.18 is found to be about 40% and 200% higher at 300 K and 77 K respectively. Measurements on transconductance enhancement are also reported. Data at 77 K provide evidence of two channels and a large enhancement of mobility at high transverse field.