Cognitive Radio Concept and Challenges in Dynamic Spectrum Access for the Future Generation Wireless Communication Systems

Recently, the Dynamic Spectrum Access (DSA) techniques are proposed to solve the problem of spectrum scarcity and help to use the limited spectrum resource as effectively as possible. The current ongoing spectrum reform opens up the possibilities to exploit the DSA techniques. This paper aims to provide a critical review on the various ongoing efforts towards the use of DSA concept for the frequency management of future wireless communications systems, especially from the Cognitive Radio (CR) perspective. The CR aims for an efficient and dynamic access to the spectrum, and provides a new method of spectrum management. This paper also highlights the various challenges associated with CR in order to realize the concept of DSA.     

Automatic Image Annotation Based on Generalized Relevance Models

This paper presents a generalized relevance model for automatic image annotation through learning the correlations between images and annotation keywords. Different from previous relevance models that can only propagate keywords from the training images to the test ones, the proposed model can perform extra keyword propagation among the test images. We also give a convergence analysis of the iterative algorithm inspired by the proposed model. Moreover, to estimate the joint probability of observing an image with possible annotation keywords, we define the inter-image relations through proposing a new spatial Markov kernel based on 2D Markov models. The main advantage of our spatial Markov kernel is that the intra-image context can be exploited for automatic image annotation, which is different from the traditional bag-of-words methods. Experiments on two standard image databases demonstrate that the proposed model outperforms the state-of-the-art annotation models.     

Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory

Bit faults induced by single-event upsets in instruction may not cause a system to experience an error. The instruction vulnerability factor (IVF) is first defined to quantify the effect of non-effective upsets on program reliability in this paper; and the mean time to failure (MTTF) model of program memory is then derived based on IVF. Further analysis of MTTF model concludes that the MTTF of program memory using error correcting code (ECC) and scrubbing is not always better than unhardened program memory. The constraints that should be met upon utilizing ECC and scrubbing in program memory are presented for the first time, to the best of authors’ knowledge. Additionally, the proposed models and conclusions are validated by Monte Carlo simulations in MATLAB. These results show that the proposed models have a good accuracy and their margin of error is less than 3 % compared with MATLAB simulation results. It should be highlighted that our conclusions may be used to contribute to selecting the optimal fault-tolerant technique to harden the program memory.     

On a Non-linear Electronic Circuit Filtering

The stochastic versions of non-linear dynamic circuits are formalized using non-linear stochastic differential equations. Stochastic differential equations (SDEs) are exploited to analyse dynamical systems in noisy environments. A potential application of the SDEs can be regarded as ‘stochastic processes in electronic circuits’. The noisy sampling mixer, a component of digital wireless communications, is an appealing and standard case from the dynamical systems’ viewpoint. It assumes the structure of a non-linear SDE, and its linearized version becomes time-varying bilinear SDE. This paper derives the filtering equations for the noisy non-linear sampling mixer circuit utilizing the filtering density evolution equation. The filtering model for the stochastic problem of concern here comprises the following: (1) a non-linear SDE describing the noisy sampling mixer and (2) a non-linear noisy observation equation. It is interesting to note that the filtered estimate accounts for observations. On the other hand, the predicted estimate does not account for the observation terms in evolution equations. As a result of this, the filtered estimate confirms the greater accuracy of estimated state trajectory in contrast to the predicted trajectory. The filtering equation of this paper can be further utilized for control of the noisy sampling mixer, where the observations are available.     

Low-Delay Parallel Architecture for Fractal Image Compression

This paper presents an efficient hardware architecture for implementing fractal image compression (FIC) algorithm aimed toward image compression with improved encoding speed. The proposed architecture follows the full-search-based FIC scheme. Parallel processing has been effectively used in the present work to achieve the goal of reducing the time complexity of the encoder. This architecture requires a total of \(2n+2\) clock cycles for executing the set of operations consisting of fetching the pixels, calculating the mean of range and domain blocks and doing their mapping, computing the error, and storing the fractal parameter in a memory with n number of pixels in the range block. Further, this architecture does not make use of any preprocessing operations as specified in literature and utilizes the benefits of isometric transformation without requiring additional cycles for every single matching operation. Effective application of isometric transformation has also led to memory reduction of nearly 67 %. Again, in the present work, the use of multipliers has been avoided to save the chip area, to reduce hardware complexity, and to enhance the encoding speed. The operation of transforming contracted domain block with a zero-mean domain block has facilitated relatively fast convergence at the decoder. PSNR above 30dB for a range block of size \(4\times 4\) has been achieved by the proposed architecture, which is comparable to that realizable by other architectures. The proposed design has been coded in Verilog HDL, has been implemented in Xilinx Virtex-5 FPGA, and operates at a clock frequency of 75.52 MHz.     

Adaptive Threshold Detection and Estimation of Linear Frequency-Modulated Continuous-Wave Signals Based on Periodic Fractional Fourier Transform

The fractional Fourier transform (FRFT) has been used to detect and estimate the parameters of linear frequency-modulated continuous-wave (LFMCW) in low probability of intercept radar waveforms. The FRFT, which is optimal for single linear frequency-modulated (LFM) signals, becomes sub-optimal when applied to LFMCW signals because the observed waveform of this type of signal is composed of concatenated LFM pulses. A new signal processing method, called the periodic FRFT (PFRFT), is proposed for the detection of LFMCW signals. First, the discrete PFRFT is studied and the signal processing gain of this transform for LFMCW signals is analyzed. Second, an adaptive threshold detection and estimation algorithm for LFMCW signals is formulated after analysis of the test statistics of the squared modulus of LFMCW signals when using the probability density function in the presence of Gaussian white noise. It is then proved that PFRFT-based estimation is equivalent to maximum likelihood estimation in the detection and estimation of LFMCW signals. Finally, the results of both the theoretical analysis and verification simulations show that the PFRFT significantly outperforms the FRFT for LFMCW signals.     

Second-Order Consensus of Multi-agent Systems via Periodically Intermittent Pinning Control

In this paper, we investigate the leader-following consensus of second-order multi-agent systems with nonlinear dynamics and time delay by employing periodically intermittent pinning control. All member agents and the virtual leader share the same nonlinear dynamics relating to the velocity and delayed velocity information. Based on Lyapunov stability theory, we obtain a novel criterion that is independent of the time delay and control width to guarantee the second-order consensus of multi-agent systems with time delay and periodically intermittent controllers. Numerical simulations are presented to illustrate the theoretical results.     

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of \({\pm }0.2\,\hbox {V}\). To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to \(250\,{\upmu }\mathrm{A}\) with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as \(240\,\Omega \) and \(19.5\,\hbox {G}\Omega \), respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC \(0.18\,\upmu \mathrm{m}\) technology.     

Unfalsified Adaptive PID Control for Time-Varying Systems Using a Fading Memory Cost Function

In this paper, we present a new cost function based on fading memory and time-window in order to decrease the influence of old data in unfalsified adaptive control applications, where the plant varies slowly or changes suddenly with time. Based on the unfalsified adaptive PID control, and the linear increasing cost-level algorithm (LICLA) switching algorithm, the new cost function can guarantee that the switching will stop and the system is stable. A systematic analysis of the system stabilization has been given. The simulation results show that without any prior knowledge of the system plant, when the current controller inserted in the system cannot guarantee the stability of the system, the cost function with a fading memory can detect the instability more quickly and then switch into a new stabilizing controller faster than the original cost function.     

Design and Performance Study of Dynamic Fractors in Any of the Four Quadrants

A fractor is a simple fractional-order system. Its transfer function is \(1/Fs^{\alpha }\); the coefficient, F, is called the fractance, and \(\alpha \) is called the exponent of the fractor. This paper presents how a fractor can be realized, using RC ladder circuit, meeting the predefined specifications on both F and \(\alpha \). Besides, commonly reported fractors have \(\alpha \) between 0 and 1. So, their constant phase angles (CPA) are always restricted between \(0^{\circ }\) and \(-90^{\circ }\). This work has employed GIC topology to realize fractors from any of the four quadrants, which means fractors with \(\alpha \) between \(-\)2 and +2. Hence, one can achieve any desired CPA between \(+180^{\circ }\) and \(-180^{\circ }\). The paper also exhibits how these GIC parameters can be used to tune the fractance of emulated fractors in real time, thus realizing dynamic fractors. In this work, a number of fractors are developed as per proposed technique, their impedance characteristics are studied, and fractance values are tuned experimentally.