Merocyanine/C60 Planar Heterojunction Solar Cells: Effect of Dye Orientation on Exciton Dissociation and Solar Cell Performance

In this study the charge dissociation at the donor/acceptor heterointerface of thermally evaporated planar heterojunction merocyanine/C₆₀ organic solar cells is investigated. Deposition of the donor material on a heated substrate as well as post‐annealing of the complete devices at temperatures above the glass transition temperature of the donor material results in a twofold increase of the fill factor. An analytical model employing an electric‐field‐dependent exciton dissociation mechanism reveals that geminate recombination is limiting the performance of as‐deposited cells. Fourier‐transform infrared ellipsometry shows that, at temperatures above the glass transition temperature of the donor material, the orientation of the dye molecules in the donor films undergoes changes upon annealing. Based on this finding, the influence of the dye molecules’ orientations on the charge‐transfer state energies is calculated by quantum mechanical/molecular mechanics methods. The results of these detailed studies provide new insight into the exciton dissociation process in organic photovoltaic devices, and thus valuable guidelines for designing new donor materials.     

Fiber Bragg Gratings in Small-Core Ge-Doped Photonic Crystal Fibers

This paper reports fiber Bragg gratings （FBGs） inscribed in a small-core Ge-doped photonic crystal fibers with a UV laser and a Talbot interferometer. The responses of such FBGs to temper- ature, strain, bending, and transverse-loading were systematically investigated. The Bragg wavelength of the FBGs shifts toward longer wavelengths with increasing temperature, tensile strain, and transverse-loading. The bending and transverse- loading properties of the FBGs are sensitive to the fiber orientations.     

SCR operation mode of diode strings for ESD protection

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thorough calibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings under static and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string are regarded, exploited and optimised.     

Automatic correction of registration errors in surgical navigation systems

Surgical navigation systems are used widely among all fields of modern medicine, including, but not limited to ENT- and maxillofacial surgery. As a fundamental prerequisite for image-guided surgery, intraoperative registration, which maps image to patient coordinates, has been subject to many studies and developments. While registration methods have evolved from invasive procedures like fixed stereotactic frames and implanted fiducial markers toward surface-based registration and noninvasive markers fixed to the patient's skin, even the most sophisticated registration techniques produce an imperfect result. Due to errors introduced during the registration process, the projection of navigated instruments into image data deviates up to several millimeter from the actual position, depending on the applied registration method and the distance between the instrument and the fiducial markers. We propose a method that allows to automatically and continually improve registration accuracy during intraoperative navigation after the actual registration process has been completed. The projections of navigated instruments into image data are inspected and validated by the navigation software. Errors in image-to-patient registration are identified by calculating intersections between the virtual instruments' axes and surfaces of hard bone tissue extracted from the patient's image data. The information gained from the identification of such registration errors is then used to improve registration accuracy by adding an additional pair of registration points at every location where an error has been detected. The proposed method was integrated into a surgical navigation system based on paired points registration with anatomical landmarks. Experiments were conducted, where registrations with deliberately misplaced point pairs were corrected with automatic error correction. Results showed an improvement in registration quality in all cases.     

Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz

It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz.     

Dirty RF: A New Paradigm

The implementation challenge for new low-cost low-power wireless modem transceivers has continuously been growing with increased modem performance, bandwidth, and carrier frequency. Up to now we have been designing transceivers in a way that we are able to keep the analog (RF) problem domain widely separated from the digital signal processing design. However, with today’s deep sub-micron technology, analog impairments – “dirt effects” – are reaching a new problem level which requires a paradigm shift in the design of transceivers. Examples of these impairments are phase noise, non-linearities, I/Q imbalance, ADC impairments, etc. In the world of “Dirty RF” we assume to design digital signal processing such that we can cope with a new level of impairments, allowing lee-way in the requirements set on future RF sub-systems. This paper gives an overview of the topic and presents analytical evaluations of the performance losses due to RF impairments as well as algorithms that allow to live with imperfect RF by compensating the resulting error effects using digital baseband processing.     

高音、微型及号筒扬声器单元的大信号性能

6．2号筒压缩式驱动器（单元） 这是一个用酚醛树脂含浸的织物为振膜的号筒压缩式单元,音圈直径51nm,卷线高度4．6mm,气隙厚4mm。连接的号筒和相位塞被移走,后腔体积仔细地密封好以避免任何额外的声学共振。     

Assessment of the Analytical Capabilities of Scanning Capacitance and Scanning Spreading Resistance Microscopy Applied to Semiconductor Devices

In this work we compare the performance of Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy for the characterization of doping profiles in semiconductor devices. Particular attention is devoted to parameters of paramount importance for the failure analysis and the characterization of silicon devices, like the quantitative one-dimensional profiling accuracy, the electrical junction delineation and the two-dimensional sub-micron imaging capability.     

Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.