The process window of a-Si/Ti bilayer metallization for anoxidation-resistant and self-aligned TiSi2 process

The dependences of both oxidation-resistant and self-aligned silicidation properties on the thicknesses of top amorphous-Si (a-Si) and Ti metal in an a-Si/Ti bilayer process are presented. It is shown that a thin silicide layer formed during the reaction between a-Si and Ti films becomes a stable oxidation and nitridation barrier for oxygen- and nitrogen-related impurities. Moreover, the formation sequence of the silicide phase depends not only on the annealing temperature but also on the thickness of the Ti film. In addition, the preferential orientation of the silicide phase after annealing at high temperature also shows a strong dependence on the thickness of Ti film, which is attributed to the difference of the grain size in the polycrystalline silicide film. The allowed process window for the a-Si thickness can be determined experimentally and a reproducible and homogeneous self-aligned TiSi₂ film can be easily obtained by using the a-Si/Ti bilayer process in salicide applications despite high-level contaminations of oxygen impurities in both the as-deposited Ti film and the annealing ambient     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

Historical review of OCR research and development

Research and development of OCR systems are considered from a historical point of view. The historical development of commercial systems is included. Both template matching and structure analysis approaches to R&D are considered. It is noted that the two approaches are coming closer and tending to merge. Commercial products are divided into three generations, for each of which some representative OCR systems are chosen and described in some detail. Some comments are made on recent techniques applied to OCR, such as expert systems and neural networks, and some open problems are indicated. The authors' views and hopes regarding future trends are presented     

Computer recognition of unconstrained handwritten numerals

Four independently, developed expert algorithms for recognizing unconstrained handwritten numerals are presented. All have high recognition rates. Different experimental approaches for incorporating these recognition methods into a more powerful system are also presented. The resulting multiple-expert system proves that the consensus of these methods tends to compensate for individual weaknesses, while preserving individual strengths. It is shown that it is possible to reduce the substitution rate to a desired level while maintaining a fairly high recognition rate in the classification of totally unconstrained handwritten ZIP code numerals. If reliability is of the utmost importance, substitutions can be avoided completely (reliability=100%) while retaining a recognition rate above 90%. Results are compared with those for some of the most effective numeral recognition systems found in the literature     

Deep-submicrometer large-angle-tilt implanted drain (LATID)technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n^- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n⁺ implant by sidewall spacers to suppress the n⁺-gate overlap to zero while keeping the n^- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed     

Modal dispersion control and distortion suppression of picosecondpulses in suspended coplanar waveguides

The propagation and dispersion characteristics of picosecond electrical pulses in a suspended coplanar waveguide (SCPW) are investigated, and it is shown that the SCPW is a very promising transmission structure for ultrashort pulses. Numerical results for the modal dispersion of the SCPW are presented and compared to those of the conventional CPW, and a field-coupling theory is used to explain the evolution in the dispersion behavior. An evaluation based on the numerical analysis shows that a SCPW with properly controlled dispersion can exhibit a five times improvement in pulse transmission capability compared to the conventional CPW. Both computer simulations and experimental measurements show a substantial suppression in pulse distortion as well, compared to conventional CPWs     

Optimization of grating duty factor in gain-coupled DFB lasers withabsorptive grating-analysis and fabrication

Grating duty factor strongly affects the performance of gain-coupled (GC) distributed feedback (DFB) laser diodes with an absorptive grating. Through numerical analysis the authors have found an optimum value in the duty factor for their low threshold operation. The minimum threshold gain achievable at this optimum duty factor is found to be almost independent of the order of the grating. According to this prediction, the authors have fabricated GaAlAs/GaAs GC DFB lasers with a third-order absorptive grating where the grating duty factor has been made close to the theoretical optimum value. In 200-μm-long devices with both facets as-cleaved, low CW threshold current of 25 mA, external efficiency of 0.5 mW/mA, and SMSR as high as 45 dB have been obtained, which is qualitatively consistent with the analysis. High yield of single mode oscillation seems to be the result of the gain coupling     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

A computational method for the LU decomposition of rectangularmatrices and its implications to the realization of 2-D digital filters

The realization of 2-D digital filters based on the lower-upper triangular decomposition of the coefficient matrix is investigated. A numerical method based on the QA decomposition, which has some important characteristics, is proposed for reaching the LU structure. The coefficients in the final LU structure have values favorable to fixed-point arithmetic implementation. Furthermore, the QR structure can be used for the realization and possesses good numerical characteristics in terms of the approximate decomposition scheme. The symmetry in the impulse response coefficient matrix of an octagonally symmetric 2-D FIR filter is utilized to reduce the computational effort spent in the decomposition and the total number of multipliers in the final realization structure