Growth of HgSe and Hg1−xCdxSe thin films by molecular beam epitaxy

Thin epitaxial films of HgSe and Hg_1−xCd_xSe (x≤0.34) were successfully grown for the first time by molecular beam epitaxy. Film growth parameters are discussed, and results of structural, electrical, and optical studies are reported.     

A single-bit-line cross-point cell activation (SCPA) architecturefor ultra-low-power SRAM's

This paper describes a single-bit-line cross-point cell activation (SCPA) architecture, which has been developed to reduce active power consumption and to avoid increase in the size of high-density SRAM chips, such as 16-Mb SRAM's and beyond. A new PMOS precharging boost circuit, introduced to realize the single-bit-line structure, is also discussed. This circuit is suitable for operation under low-voltage power supply conditions. The SCPA architecture with the new word-line boost circuit is demonstrated with the experimental device, which is fabricated by a 0.4-μm CMOS wafer process technology     

Relationship between dipole parameter estimation errors andmeasurement conditions in magnetoencephalography

In this study, a model in a computer simulation uses a single current dipole in a spherical homogeneous medium. Dipole parameters are estimated using a moving dipole procedure. Signal-to-noise ratio (SNR) is defined as the square-root of the ratio of the average signal power to the average noise power over all measurement points. At SNR>20, accurate estimation can be carried out independently of dipole depth and coil size. At SNR<20, dipole depth influences estimation error. When the dipole is located near the center of the sphere, the measurement region should include both extrema of the magnetic field to minimize estimation error. However, when the dipole is not so deep, the position of the measurement region does not influence estimation error. When SNR<4, estimation error increases as coil size increases. Coil size minimizing estimation error is determined by the ratio of environmental magnetic field noise to electrical noise. For a constant size of measurement region, increasing the number of measurement points decreases estimation error to a certain level. This error level depends on SNR     

Optical power equalization for multiwavelength fiber-amplifiercascades using periodic inhomogeneous broadening

Inhomogeneously broadened fiber amplifiers inserted periodically in an amplifier cascade are shown to provide significant interchannel power equalization in wavelength-multiplexed systems. Interchannel power variations in a six-amplifier cascade are reduced from 16 dB in a conventional system to about 5 dB when power equalizers are inserted     

A study and optoelectronic verification of AlGaAs/GaAsheterojunction bipolar transistor large-signal characteristics

A hybrid optoelectronic measurement system is constructed and used to obtain the large-signal characteristics of AlGaAs/GaAs heterojunction bipolar transistors. The measurement system utilizes a terahertz-bandwidth electrooptic transducer gated by 100-fs laser pulses to interrogate the time-domain waveforms at the device input and output nodes. A microwave signal phase-locked to the laser pulse-train is used to synchronously excite the device in both small-signal and large-signal regimes. The measurement system is capable of 50-GHz bandwidth and provides time-domain voltage waveforms that can be used directly to verify the time-domain results of the large-signal analysis     

Hot-carrier degradation of submicrometer p-MOSFETs withthermal/LPCVD composite oxide

It is shown that while gate oxides containing thermal/LPCVD composite oxide have lower defect densities than gates using only thermal oxides, they are more susceptible to hot-carrier degradation. The hot-carrier-induced degradation of composite oxides is worse in p-channel MOSFETs than in n-channel MOSFETs. This sensitivity of p-channel MOSFETs is caused by higher electron trapping levels in LPCVD oxides. For 150-Å gate technology, the hot-carrier-degradation resistance of thermal/LPCVD composite gate oxides with a 70-Å or thicker thermal oxide layer approaches that of high-quality pure thermal oxide     

Simulation and fabrication of submicron channel length DMOStransistors for analog applications

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1-μm-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7° implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t_si; gate oxide thickness t_ox) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 μm while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator     

Singlemode surface emitting laser using partial mirror disordering

A vertical cavity surface emitting semiconductor laser is described which uses zinc diffusion and partial disordering of the epitaxial output mirror to provide waveguiding for lateral mode control. Mode suppression ratios against higher order transverse modes as high as 36 dB have been observed.<>