The First Template‐Free Growth of Crystalline Silicon Microtubes

A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications.     

Moving Least-Squares Differential Quadrature Method for Free Vibration of Antisymmetric Laminates

In this paper, the moving least-squares differential quadrature (MLSDQ) method is employed for free vibration of thick antisymmetric laminates based on the first-order shear deformation theory. The generalized displacements of the laminates are independently approximated with the centered moving least-squares (MLS) technique within each domain of influence. The MLS nodal shape functions and their partial derivatives are computed quickly through back-substitutions after only one LU decomposition. Subsequently, the weighting coefficients in the MLSDQ discretization are determined with the nodal partial derivatives of the MLS shape functions. The MLSDQ method combines the merits of both the differential quadrature and meshless methods which can be conveniently applied to complex domains and irregular discretizations without loss of implementation efficiency and numerical accuracy. The natural frequencies of the laminates with various edge conditions, ply angles, and shapes are calculated and compared with the existing solutions to study the numerical accuracy and stability of the MLSDQ method. Effects of support size, order of completeness of basis functions, and node irregularity on the numerical accuracy are investigated in detail.     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

Low-temperature poly-SiGe alloy growth of high gain/speed pin infrared photosensor with gold-induced lateral crystallization (Au-ILC)

The hydrogenated poly-silicon germanium (poly-SiGe:H) epitaxial film has been investigated using gold-induced lateral crystallization (Au-ILC) technology on a-SiGe:H layers at 10-h 350/spl deg/C annealing temperature and 60-sccm hydrogen (H/sub 2/) content. Using this optimal condition, the growth rate of the induced Au was as large as 15.9 /spl mu/m/h. With a low annealing temperature (/spl les/400/spl deg/C) and large growth rate, this novel technology will be noticeably useful for poly-SiGe:H pin IR-sensing fabrication on a conventional precoated indium tin oxide (ITO)-glass substrate. Under a 1-/spl mu/W IR-LED incident light (with peak wave length at 710 nm) and at a 5-V biased voltage, the poly-SiGe:H pin IR sensor developed by the Au-ILC technology, i.e., an Al (anode)/n poly-SiGe:H/i poly-SiGe:H/p poly-SiGe:H/ITO (cathode)/glass-substrate structure allowed for maximum optical gain and response speed. The optical gains and the response speeds were almost 600 and 130%, respectively, better than that of a traditional pin type. Meanwhile, the FWHM of a poly-SiGe:H pin sensor with Au-ILC technology was reduced from 280 to 150 nm. This reveals excellent IR-sensing selectivity. These IR-sensing trials demonstrated again that the proposed Au-ILC technology has very useful application in the field of low cost integrated circuits on optoelectronic applications.     

化学复合镀层激光处理研究

研究了激光处理对Ni-P -SiC化学复合镀层的影响。借助于扫描电镜、能谱仪、X射线衍射、显微硬度计等设备对激光处理后复合镀层的表面形貌、组织结构及性能进行了综合分析。结果表明 ,对复合镀层进行激光处理可以获得与炉内加热同样的镀层硬度 ,且当激光功率 4 0 0W ,扫描速度 1.5m /min时 ,镀层硬度高于炉内加热的硬度     

Fringing in tubular permanent-magnet machines: Part I. Magnetic field distribution, flux linkage, and thrust force

This paper extends an analysis developed for tubular permanent-magnet machines to account for the effect of fringing associated with the finite length of the ferromagnetic armature core. The magnetic field distribution, established by using an analytical technique formulated in the cylindrical coordinate system, provides an accurate means of evaluating the effect of the fringing flux on the thrust force and the back-electromotive force. Finite-element calculations confirm the analytically derived results. In Part II of the paper, the analysis is used to predict the cogging force that results from end effects and to facilitate minimization of the force.     

单元串联式多电平高压变频器的起源、现状和展望

本文对单元串联式多电平高压变频器的起源和现状进行了总结,同时从无速度传感器矢量控制、大容量化、冗余设计等方面对该技术未来的发展趋势进行了展望。     

Optimised anaerobic treatment of house-sorted biodegradable waste and slaughterhouse waste in a high loaded half technical scale digester.

Anaerobic co-digestion of organic wastes from households, slaughterhouses and meat processing industries was optimised in a half technical scale plant. The plant was operated for 130 days using two different substrates under organic loading rates of 10 and 12 kgCOD.m(-3).d(-1). Since the substrates were rich in fat and protein components (TKN: 12 g.kg(-1) the treatment was challenging. The process was monitored on-line and in the laboratory. It was demonstrated that an intensive and stable co-digestion of partly hydrolysed organic waste and protein rich slaughterhouse waste can be achieved in the balance of inconsistent pH and buffering NH4-N. In the first experimental period the reduction of the substrate COD was almost complete in an overall stable process (COD reduction >82%). In the second period methane productivity increased, but certain intermediate products accumulated constantly. Process design options for a second digestion phase for advanced degradation were investigated. Potential causes for slow and reduced propionic and valeric acid degradation were assessed. Recommendations for full-scale process implementation can be made from the experimental results reported. The highly loaded and stable codigestion of these substrates may be a good technical and economic treatment alternative.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.