全文获取类型
收费全文 | 3142篇 |
免费 | 50篇 |
国内免费 | 8篇 |
专业分类
电工技术 | 97篇 |
化学工业 | 581篇 |
金属工艺 | 107篇 |
机械仪表 | 39篇 |
建筑科学 | 47篇 |
能源动力 | 68篇 |
轻工业 | 237篇 |
水利工程 | 3篇 |
石油天然气 | 4篇 |
无线电 | 339篇 |
一般工业技术 | 549篇 |
冶金工业 | 907篇 |
原子能技术 | 84篇 |
自动化技术 | 138篇 |
出版年
2023年 | 9篇 |
2022年 | 40篇 |
2021年 | 42篇 |
2020年 | 12篇 |
2019年 | 15篇 |
2018年 | 31篇 |
2017年 | 33篇 |
2016年 | 39篇 |
2015年 | 26篇 |
2014年 | 55篇 |
2013年 | 92篇 |
2012年 | 82篇 |
2011年 | 114篇 |
2010年 | 72篇 |
2009年 | 98篇 |
2008年 | 102篇 |
2007年 | 106篇 |
2006年 | 93篇 |
2005年 | 90篇 |
2004年 | 96篇 |
2003年 | 92篇 |
2002年 | 87篇 |
2001年 | 58篇 |
2000年 | 57篇 |
1999年 | 60篇 |
1998年 | 373篇 |
1997年 | 212篇 |
1996年 | 152篇 |
1995年 | 94篇 |
1994年 | 121篇 |
1993年 | 93篇 |
1992年 | 41篇 |
1991年 | 44篇 |
1990年 | 47篇 |
1989年 | 42篇 |
1988年 | 40篇 |
1987年 | 35篇 |
1986年 | 33篇 |
1985年 | 41篇 |
1984年 | 15篇 |
1983年 | 20篇 |
1982年 | 24篇 |
1981年 | 13篇 |
1980年 | 15篇 |
1979年 | 17篇 |
1978年 | 14篇 |
1977年 | 14篇 |
1976年 | 43篇 |
1975年 | 13篇 |
1972年 | 9篇 |
排序方式: 共有3200条查询结果,搜索用时 46 毫秒
21.
Polarization-controlled single-mode VCSEL 总被引:2,自引:0,他引:2
Yoshikawa T. Kawakami T. Saito H. Kosaka H. Kajita M. Kurihara K. Sugimoto Y. Kasahara K. 《Quantum Electronics, IEEE Journal of》1998,34(6):1009-1015
Relative intensity noise (RIN) in a vertical-cavity surface-emitting laser (VCSEL) was greatly reduced through the use of polarization control to eliminate competition between two orthogonal polarization states by ensuring there was only one polarization state. Polarization was stable with optical feedback of up to 10%. Polarization control was achieved by inducing a small loss anisotropy in fundamental transversal mode VCSEL's. Anisotropic post structures, such as a rectangular post, an oblique post, or a zigzag-sidewall post, were found to be effective in creating loss anisotropy without serious degradation of other VCSEL characteristics such as light-output power or beam profile 相似文献
22.
Yoshitomi T. Saito M. Ohguro T. One M. Momose H.S. Morifuji E. Morimoto T. Katsumata Y. Iwai H. 《Electron Devices, IEEE Transactions on》1998,45(6):1295-1299
A silicided silicon-sidewall source and drain (S4D) structure is proposed for sub-0.1-μm devices. The merit of the S4D structure is that the series resistance of the source and drain is significantly reduced since the silicide layer is attached very close to the gate electrode and the silicon sidewall can be doped very highly. Thus, very high drain current drive can be expected, Another advantage of this structure is that the source and drain extensions are produced by the solid-phase diffusion of boron from the highly doped silicon-sidewall. Thus, shallow extensions with very high doping can be realized. A 75-nm gate length pMOSFET fabricated with this structure is shown to exhibit excellent electrical characteristics 相似文献
23.
Ultra-fine space pattern printing by Synchrotron Radiation x-ray lithography was investigated. New types of cross-sectioned mask1) were used to overcome the difficulty of mask fabrication. As a result, feasibility to print space patterns with a width of 50 nm or less by contact printing was demonstrated. In practice, a very narrow mask-to-wafer gap setting and precise control of the x-ray irradiation angle are necessary. 相似文献
24.
K. Maruyama H. Nishino T. Okamoto S. Murakami T. Saito Y. Nishijima M. Uchikoshi M. Nagashima H. Wada 《Journal of Electronic Materials》1996,25(8):1353-1357
(lll)B CdTe layers free of antiphase domains and twins were directly grown on (100) Si 4°-misoriented toward<011> substrates,
using a metalorganic tellurium (Te) adsorption and annealing technique. Direct growth of (lll)B CdTe on (100) Si has three
major problems: the etching of Si by Te, antiphase domains, and twinning. Te adsorption at low temperature avoids the etching
effect and annealing at a high temperature grows single domain CdTe layers. Te atoms on the Si surface are arranged in two
stable positions, depending on annealing temperatures. We evaluated the characteristics of (lll)B CdTe and (lll)B HgCdTe layers.
The full width at half maximum (FWHM) of the x-ray double crystal rocking curve (DCRC) showed 146 arc sec at the 8 |im thick
CdTe layers. In Hg1−xCdxJe (x = 0.22 to 0.24) layers, the FWHMs of the DCRCs were 127 arc sec for a 7 (im thick layer and 119 arc sec for a 17 (im
thick layer. The etch pit densities of the HgCdTe were 2.3 x 106 cm2 at 7 ^m and 1.5 x 106 cm-2 at 17 um. 相似文献
25.
H. Ebe T. Okamoto H. Nishino T. Saito Y. Nishijima M. Uchikoshi M. Nagashima H. Wada 《Journal of Electronic Materials》1996,25(8):1358-1361
CdTe epilayers were grown directly on (100), (211), and (111) silicon substrates by metalorganic chemical vapor deposition
(MOCVD). The crystallinity and the growth orientation of the CdTe film were dependent on the surface treatment of the Si substrate.
The surface treatment consisted of exposure of the Si surface to diethyltelluride (DETe) at temperatures over 600°C prior
to CdTe growth. Direct growth of CdTe on (100) Si produced polycrystalline films whereas (lll)B single crystals grew when
Si was exposed to DETe prior to CdTe growth. On (211) Si, single crystal films with (133)A orientation was obtained when grown
directly; but produced films with (211)A orientation when the Si surface was exposed to DETe. On the other hand, only (lll)A
CdTe films were possible on (111) Si, both with and without Te source exposure, although twinning was increased after exposure.
The results indicate that the exposure to a Te-source changes the initial growth stage significantly, except for the growth
on (111) Si. We propose a model in which a Te atom replaces a Si atom that is bound to two Si atoms. 相似文献
26.
1.5 nm direct-tunneling gate oxide Si MOSFET's 总被引:6,自引:0,他引:6
Sasaki H. Ono M. Yoshitomi T. Ohguro T. Nakamura S. Saito M. Iwai H. 《Electron Devices, IEEE Transactions on》1996,43(8):1233-1242
In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used 相似文献
27.
Hirose T. Saito K. Kojima S. Yao B. Ohsono K. Sato S. Takada K. Ikushima A.J. 《Electronics letters》2007,43(8):443-445
Long-period fibre grating (LPFG) writing by a CO2 laser-annealing using a fibre-drawing process is demonstrated. The fibre in the drawing process was irradiated periodically by a CO2 laser to modify the refractive index. An LPFG with transmission loss of -10 dB and full width at half-maximum of 13 nm has been fabricated. Results show that the refractive index change was induced by stress at the moment of laser annealing 相似文献
28.
Nakazawa Y. Komatsu T. Saito T. 《Vision, Image and Signal Processing, IEE Proceedings -》1996,143(4):234-240
The authors propose an image processing-based approach towards the development of a super-high-resolution image acquisition system. Imaging methods based on this approach can be classified into two main categories: a spatial integration imaging method and a temporal integration imaging method. With regard to the spatial integration imaging method, the authors have previously presented a method for acquiring an improved-resolution image by integrating multiple images taken simultaneously with multiple different cameras. They develop their work, aiming at a particular class of application where a user indicates a region of interest (ROI) on an observed image in advance, and apply a prototypal temporal integration imaging method. The prototypal temporal integration imaging method does not involve global image segmentation, but uses a subpixel registration algorithm which describes an image warp within the ROI, with subpixel accuracy, as a deformation of quadrilateral patches. The method then performs a subpixel registration by warping an observed image with the warping function recovered from the deformed quadrilateral patches. Experimental simulations demonstrate that the temporal integration imaging is promising as a basic means of high resolution imaging 相似文献
29.
Keizo Uematsu Jin-Young Kim Masayori Miyashita Nozomu Uchida Katsuichi Saito 《Journal of the American Ceramic Society》1990,73(8):2555-2557
The internal structure of spray-dried alumina granules was characterized by optical microscopy by immersing them in a liquid having a refractive index close to that of alumina. This method provides a unique technique for the detailed analysis of the internal structure of spray-dried granules. 相似文献
30.
Igarashi S Haraguchi M Aihara J Saito T Yamaguchi K Yamamoto H Hojou K 《Journal of electron microscopy》2004,53(3):223-228
The formation and the phase transitions of iron silicide by solid-phase epitaxy have been investigated by means of plan-view transmission electron microscopy, which enables us to observe a clean interface between Fe and Si. Layers of Fe were deposited on Si (100) at room temperature in an ultrahigh vacuum chamber. The sample was annealed in the electron microscope at a temperature between 673 and 1073 K. After annealing at 673 K, FeSi crystallites were formed with various orientations. When the annealing temperature was increased to 973 K, we found that the crystallites suddenly started to coalesce into grains of several hundreds of nanometers in size and polycrystalline beta-FeSi2 was formed. These phase transitions were also confirmed with electron energy-loss spectroscopy. 相似文献