Enhancement of the Performance of a Reflective SOA-Based Hybrid WDM/TDM PON System With a Remotely Pumped Erbium-Doped Fiber Amplifier

A passive optical network (PON) architecture based on a hybrid wavelength-division multiplexing (WDM) and time-division multiplexing (TDM) PON system with a remotely pumped erbium-doped fiber amplifier (EDFA) is presented as an excellent candidate for use in a next-generation optical access network. The remotely pumped EDFA operates as a bidirectional amplifier and provides a 15-dB gain to both upstream signals and seed light sources, so the sensitivity of upstream transmission is greatly improved. An upstream transmission of 1.25 Gb/s with a low seed channel power of -14 dBm is made feasible over a total reach of 25 km for 32-WDM channels and 16-TDM splits by the use of the remotely pumped EDFA. This scheme has advantages that it uses a single transmission fiber for both down-and up-stream signals and that it reduces the Rayleigh scattering contribution.     

ZnO-Based Low-Voltage Inverter With Quantum-Well-Structured Nanohybrid Dielectric

We report on the fabrication of 2-V-operating ZnO-based inverter with two n-channel thin-film transistors (TFTs) on 22-nm-thin organic/inorganic nanohybrid dielectric, which contains AlO_x/TiO_x/AlO_x in triple-layer structure. The inverter shows a high voltage gain of ~20 under the supply voltage (V_DD) of 2 V but with a marginal transition voltage of 0.1 V (operation range of 0-2 V). To control the transition voltage to a more adequate value, an 8-V gate pulse was applied on driving ZnO-TFT so that some of the channel electrons would be tunneled through the AlO_x-based barrier and trapped in the TiO_x-based layer. Our inverter then displayed an optimum transition voltage of 0.75 V.     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

Direct Graphene Transfer and Its Application to Transfer Printing Using Mechanically Controlled,Large Area Graphene/Copper Freestanding Layer

Direct graphene transfer is an attractive candidate to prevent graphene damage, which is a critical problem of the conventional wet transfer method. Direct graphene transfer can fabricate the transferred graphene film with fewer defects by using a polymeric carrier. Here a unique direct transfer method is proposed using a 300 nm thick copper carrier as a suspended film and a transfer printing process by using the polydimethylsiloxane (PDMS) stamp under controlled peeling rate and modulus. Single and multilayer graphene are transferred to flat and curved PDMS target substrate directly. With the transfer printing process, the transfer yield of a trilayer graphene with 1000 µm s^?1 peeling rate is 68.6% of that with 1 µm s^?1 peeling rate. It is revealed that the graphene transfer yield is highly related to the storage modulus of the PDMS stamp: graphene transfer yield decreases when the storage modulus of the PDMS stamp is lower than a specific threshold value. The relationship between the graphene transfer yield and the interfacial shear strain of the PDMS stamp is studied by finite‐element method simulation and digital image correlation.     

Graphene-Based Ultralight Compartmentalized Isotropic Foams with an Extremely Low Thermal Conductivity of 5.75 mW m−1 K−1

The importance of high-performance thermal insulation materials is rapidly emerging due to energy conservation and the management of temperature-sensitive device perspectives. Recent thermal insulation materials including complex structures have been developed either by reducing the structural connectivity to mitigate thermal transport through solid conduction or forming directionally aligned confined inner pores to suppress the internal gas convection. In this study, to create a highly efficient thermal insulating material that suppresses thermal transport in all directions, graphene-based anisotropic closed-cellular structures (CCS) are devised with a highly ordered assembly of hollow compartments with extremely thin walls (≈50 nm). This uniquely designed CCS made from microfluidically synthesized graphene solid bubbles exhibited a remarkably low thermal conductivity of 5.75 mW m⁻¹ K⁻¹ thanks to effective suppression of both solid conduction and gas conduction/convection. Therefore, the proposed strategy in this work offers a novel toolkit for implementing next-generation high-performance insulation materials.     

A Consistent Description of Scaling Law for Flux Pinning in ${hbox{Nb}}_{3}{hbox{Sn}}$ Strands Based on the Kramer Model (Corrected)*

There are a lot of experimental reports on the scaling of flux pinning in the form of F = F_mb^1/2(1 - b)², with b = B/B_c2.The temperature dependence of F_m is approximately proportional to B'.2 , whereas the strain dependence of Fm is reported to be proportional to the upper critical field Bc2. In this work, we re-analyze our previous data with the Kramer model including the pin-breaking dynamic pinning force (F_p) for a low field region. It is shown that the extrapolated upper critical field B_c2*, strongly depend on the ratio between the mean of the parameter K_p for F_p (p>) and the parameter K, for the flux line lattice shearing pinning force F_s. It is found that the strain dependence of F_m at 4.2 K is approximately proportional to (B_c2*)^1.5. We further compare the data with the prediction of our recent scaling theory based on Eliashberg theory of strongly coupled superconductors. It is shown that the strain dependence of F_m at 4.2 K is proportional to BC₂ ^5/2 kappa^-2, consistent with the temperature dependence of Fm. Moreover, this model agrees reasonably well even with the data in a high compressive strain region (<-0.8%).     

Tracking and Coordination of Multiple Agents Using Sensor Networks: System Design, Algorithms and Experiments

This paper considers the problem of pursuit evasion games (PEGs), where the objective of a group of pursuers is to chase and capture a group of evaders in minimum time with the aid of a sensor network. The main challenge in developing a real-time control system using sensor networks is the inconsistency in sensor measurements due to packet loss, communication delay, and false detections. We address this challenge by developing a real-time hierarchical control system, named LochNess, which decouples the estimation of evader states from the control of pursuers via multiple layers of data fusion. The multiple layers of data fusion convert noisy, inconsistent, and bursty sensor measurements into a consistent set of fused measurements. Three novel algorithms are developed for LochNess: multisensor fusion, hierarchical multitarget tracking, and multiagent coordination algorithms. The multisensor fusion algorithm converts correlated sensor measurements into position estimates, the hierarchical multitarget tracking algorithm based on Markov chain Monte Carlo data association (MCMCDA) tracks an unknown number of targets, and the multiagent coordination algorithm coordinates pursuers to chase and capture evaders using robust minimum-time control. The control system LochNess is evaluated in simulation and successfully demonstrated using a large-scale outdoor sensor network deployment     

Complexity‐Reduced Algorithms for LDPC Decoder for DVB‐S2 Systems

This paper proposes two kinds of complexity‐reduced algorithms for a low density parity check(LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.     

Fabrication of high current and low profile micromachined inductorwith laminated Ni/Fe core

A new process for the fabrication of high current and very low profile micromachined inductors has been developed. This process involves the combination of mechanical lamination and electrodeposition of copper windings by means of LIGA-like lithography through thick epoxy photoresists. The dimension of the fabricated inductor is 16 mm×19 mm×1 mm. The fabricated inductor has an inductance value of 1.2 μH with DC saturation current of 3 A and an electrical resistance of less than 30 mΩ at 10 kHz     

Implementation of a third-generation 1.1-GHz 64-bit microprocessor

This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13-/spl mu/m CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.