Formation of Gold and Silver Nanoparticle Arrays and Thin Shells on Mesostructured Silica Nanofibers

Mesostructured silica nanofibers synthesized in high yields with cetyltrimethylammonium bromide as the structure‐directing agent in HBr solutions are used as templates for the assembly of Au and Ag nanoparticles and the formation of thin Au shells along the fiber axis. Presynthesized spherical Au and Ag nanoparticles are adsorbed in varying amounts onto the silica nanofibers through bifunctional linking molecules. Nonspherical Au nanoparticles with sharp tips are synthesized on the nanofibers through a seed‐mediated growth approach. The number density of nonspherical Au nanoparticles is controlled by varying the amount of seeded nanofibers relative to the amount of supplied Au precursor. This seed‐mediated growth is further used to form continuous Au shells around the silica nanofibers. Both the Au‐ and Ag‐nanoparticle/silica‐nanofiber hybrid nanostructures and silica/Au core/shell fibers exhibit extinction spectra that are distinct from the spectra of Au and Ag nanoparticles in solution, indicating the presence of new surface plasmon resonance modes in the silica/Au core/shell fibers and surface plasmon coupling between closely spaced metal nanoparticles assembled on silica nanofibers. Spherical Au‐ and Ag‐nanoparticle/silica‐nanofiber hybrid nanostructures are further used as substrates for surface‐enhanced Raman spectroscopy, and the enhancement factors of the Raman signals obtained on the Ag‐nanoparticle/silica‐nanofiber hybrid nanostructures are 2 × 10⁵ for 4‐mercaptobenzoic acid and 4‐mercaptophenol and 7 × 10⁷ for rhodamine B isothiocyanate. These hybrid nanostructures are therefore potentially useful for ultrasensitive chemical and biological sensing by using molecular vibrational signatures.     

传统中药现代化--中药健康食品的开发

传统中药是现代生活健康的宝库,其功效在保健及慢性疾病的治疗方面尤其显著,并已备受世界重视.要成功将中药引进世界市场,最基本要求是要从科学方法去证明其效用及安全性;更重要是依从传统中医学对复方应用的要求去作研究.本文陈述了我们对传统中药古方"生脉散"研究及开发抗氧化健康食品的经验.透过现代生化及药理技术,我们发现"生脉散"中的五味子含丰富的抗氧化活性成分,为传统中医学利用"生脉散"治疗心脏病提供了理论依据.     

Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

Quadrature Oscillators with Grounded Capacitors and Resistors Using FDCCIIs

Two current‐mode and/or voltage‐mode quadrature oscillator circuits each using one fully‐differential second‐generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current‐mode quadrature signals have the advantage of high‐output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current‐mode and voltage‐mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.     

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V _dd assignment, multiple V _th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.     

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Temperature affects not only the performance but also the power, reliability, and cost of the embedded system. This paper proposes a temperature-aware task allocation and scheduling algorithm for MPSoC embedded systems. Thermal-aware heuristics are developed, and a temperature-aware floorplanning tool is used to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints. The paper investigates both power-aware and thermal-aware approaches to the task allocation and scheduling. The experimental results show that the thermal-aware approach outperforms the power-aware schemes in terms of maximal and average temperature reductions. To the best of our knowledge, this is the first MPSoC task allocation and scheduling algorithm that takes temperature into consideration.

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Reliability of Au-Ge and Au-Si Eutectic Solder Alloys for High-Temperature Electronics

High-temperature electronics will facilitate deeper drilling, accessing harder-to-reach fossil fuels in oil and gas industry. A key requirement is reliability under harsh conditions for a minimum continuous operating time of 500?h at 300°C. Eutectic solder alloys are generally favored due to their excellent fatigue resistance. Performance of Au-Ge and Au-Si eutectic solder alloys at 300°C up to 500?h has been evaluated. Nanoindentation results confirm the loss of strength of Au-Ge and Au-Si eutectic solder alloys during thermal aging at 300°C, as a result of grain coarsening. However, the pace at which the Au-Ge eutectic alloy loses its strength is much slower when compared with Au-Si eutectic alloy. The interfacial reactions between these eutectic solder alloys and the underbump metallization (UBM), i.e., electroless nickel immersion gold (ENIG) UBM and Cu/Au UBM, have been extensively studied. Spalling of Au₃Cu intermetallic compound is observed at the interface between Au-Ge eutectic solder and the Cu/Au UBM, when aged at 300°C for 500?h, while the consumption of ENIG UBM is nominal. Unlike the Au-Si solder joint, hot ball shear testing at high temperature confirmed that the Au-Ge joint on ENIG UBM, when aged at 300°C for 500?h, could still comply with the minimum qualifying bump shear strength based on the UBM dimension used in this work. Thus, it has been determined that, among these two binary eutectic alloys, Au-Ge eutectic alloy could fulfill the minimum requirement specified by the oil and gas exploration industry.     

先进的企业级性能催化下一代SAS系统

引言当存储器OEM和集成厂商在引进并采用基于SAS的系统时,都会希望能够提供流量管理和安全领域所需的光纤通道及企业级特性。为满足这些需求,在即将推出的SAS 2.0规范中引入了端对端分区的概念。根据定义,SAS协议在指定的域中支持最多16384个设备(启动器、目标器、扩展器和/或虚拟设备),然而,在实际应用中,     

Upgrading service availability of optical networks: A labor force perspective

Service availability is an important issue in optical networks. Much research attention has been drawn to the provisioning of reliable connections achieved by approaches such as routing and wavelength assignment and by protection and restoration mechanisms. In contrast, the research on upgrading networks to meet new or dynamic demands of service availability based on network upgrading process has been comparatively lacking. In this paper, we address this issue by upgrading service availability from the perspective of labor forces for network maintenance. Our approach is premised on the assumption that the time period for fixing an optical link can be reduced by using more network resources of labor forces. To model this concept, we conduct Amdahl's law, a well‐known theorem in parallel computing, to describe human teamwork. To show the effectiveness of this concept, we propose mixed integer linear programming aiming at either maximizing service availability under limited labor forces or minimizing labor forces for predetermined service availability. In addition, a heuristic algorithm for upgrading service availability is presented. Our experimental results show that our network upgrading process can improve service availability optimally with a fixed number of forces and the proposed heuristic algorithm can effectively save computation time.     

A fast tag identification anti‐collision algorithm for RFID systems

In this work, we propose a highly efficient binary tree‐based anti‐collision algorithm for radio frequency identification (RFID) tag identification. The proposed binary splitting modified dynamic tree (BS‐MDT) algorithm employs a binary splitting tree to achieve accurate tag estimation and a modified dynamic tree algorithm for rapid tag identification. We mathematically evaluate the performance of the BS‐MDT algorithm in terms of the system efficiency and the time system efficiency based on the ISO/IEC 18000‐6 Type B standard. The derived mathematical model is validated using computer simulations. Numerical results show that the proposed BS‐MDT algorithm can provide the system efficiency of 46% and time system efficiency of 74%, outperforming all other well‐performed algorithms.