Cumulative balance testing of logic circuits

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation, provably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence     

On the design of fast, easily testable ALU's

A design methodology for implementing fast, easily testable arithmetic-logic units (ALUs) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either &thetas;(N) complexity (Lin-testable) or &thetas;(1) complexity (C-testable), where N is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lintestable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lintestable ALU is only 0.5%     

A comparison of electronic-reliability prediction models

One of the most controversial procedures in reliability is the use of reliability prediction techniques based on component failure data to estimate system failure rates. The International Electronics Reliability Institute (IERI) at Loughborough University is in a unique position. Over many years, much reliability information has been collected from leading British and Danish electronic manufacturing companies. These data are of such high quality that IERI can perform the comparison exercise with many circuit boards (CB) of different types. Several CB were selected from the IERI field-failure database and their reliability was predicted and compared with the observed field-performance. The prediction techniques were based on the: M217E [US Mil-Hdbk-217E]; HRD4; Siemens (SN29500); CNET; and Bellcore (TR-TSY-000332) models. For each model, the associated published failure rates were used. Hence, parts count analyses were performed on several CB from the database; these analyses were compared with the field failure rate. The prediction values differ greatly from the observed field behavior and from each other. Further analysis showed that each prediction model was sensitive to widely different physical parameters. The results are summarized. Some of the models are more sensitive to a factor that varies according to an Arrhenius model, such as temperature and electrical stress, while others are more sensitive to the discrete π factors used to model environment and quality     

Collector/emitter offset voltage in double-heterojunction bipolar transistors

Double-heterojunction bipolar transistors (DHBT) can exhibit a large collector/emitter offset voltage at zero collector current which will adversely affect digital switching circuits. It is shown that this effect results from insufficient grading at the base/collector heterojunction. A GaAlAs/GaAs DHBT grown by MBE having a 130 ? compositional grading at the emitter/base and base/collector junction showed no sign of the collector/emitter offset voltage.     

The Coupling Model for Function and Delay Faults

We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function. This research was sponsored in part by the U.S. National Science Foundation under Grants No. CCR-9872066 and CCR-0073406. Joonhwan Yi received the B.S degree in electronics engineering from Yonsei University, Seoul, Korea, in 1991, and the M.S. and Ph.D degrees in electrical engineering and computer science from the University of Michigan, Ann Arbor, in 1998 and 2002, respectively. From 1991 to 1995, he was with Samsung Electronics, Semiconductor Business, Korea, where he was involved in developing application specific integrated circuit cell libraries. In 2000, he was a summer intern with Cisco, Santa Clara, CA, where he worked for path delay fault testing. Since 2003, he has been with Samsung Electronics, Telecommunication Network, Suwon, Korea, where he is working on system-on-a-chip design. His current research interests include C-level system modeling for fast hardware and software co-simulation, system-level power analysis and optimization, behavioral synthesis, and high-level testing. John P. Hayes received the B.E. degree from the National University of Ireland, Dublin, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign, all in electrical engineering. While at the University of Illinois, he participated in the design of the ILLIAC III computer. In 1970 he joined the Operations Research Group at the Shell Benelux Computing Center in The Hague, where he worked on mathematical programming and software development. From 1972 to 1982 he was a faculty member of the Departments of Electrical Engineering– Systems and Computer Science of the University of Southern California, Los Angeles. Since 1982 he has been with the Electrical Engineering and Computer Science Department of the University of Michigan, Ann Arbor, where he holds the Claude E. Shannon Chair in Engineering Science. Professor Hayes was the Founding Director of the University of Michigan's Advanced Computer Architecture Laboratory (ACAL). He has authored over 225 technical papers, several patents, and five books, including Introduction to Digital Logic Design (Addison-Wesley, 1993), and Computer Architecture and Organization, (3rd edition, McGraw-Hill, 1998). He has served as editor of various technical journals, including the Communications of the ACM, the IEEE Transactions on Parallel and Distributed Systems and the Journal of Electronic Testing. Professor Hayes is a fellow of both IEEE and ACM, and a member of Sigma Xi. He received the University of Michigan's Distinguished Faculty Achievement Award in 1999 and the Humboldt Foundation's Research Award in 2004. His current teaching and research interests are in the areas of computer-aided design, verification, and testing; VLSI circuits; fault-tolerant embedded systems; ad-hoc computer networks; and quantum computing.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Origin of petroporphyrins. 2. Evidence from stable carbon isotopes

Compared with the carbon-13 isotopic composition of the ubiquitous C32DPEP (DPEP, deoxophylloerythroetioporphyrin) the heavy but equivalent carbon-13 isotopic composition for the porphyrin structures 15(2)-methyl-15,17-ethano-17-nor-H-C30DPEP and 15,17-butano-, 13,15-ethano-13(2),17-propano-, and 13(1)-methyl-13,15-ethano-13(2),17-propanoporphyrin suggests a common precursor, presumably chlorophyll c, for these petroporphyrins isolated from the marine Julia Creek oil shale and the lacustrine Condor oil shale. Similarly, the heavy but variable carbon-13 isotopic composition of 7-nor-H-C31DPEP compared with C32DPEP is consistent with an origin from both chlorophyll b and chlorophyll c3. The equivalent carbon-13 isotopic composition for 13(2)-methyl-C33DPEP compared with C32DPEP suggests a common origin resulting from a weighted average of chlorophyll inputs.     

Approaches for introducing TMN in legacy networks: a critical look

Introducing the telecommunications management network (TMN) into a legacy network is generally an uphill battle. This article provides a critical review of the two key approaches used in the industry for introducing TMN interfaces into legacy networks. Before the analysis, it is of prime importance to establish some ground rules. There is currently no common understanding of what introducing TMN into a legacy network means, as there is no common understanding of what introducing TMN into a network means. We start by analyzing what introducing TMN into a legacy network means, and then study, successively, the bottom-up and top-down approaches. Finally, a cost trade-off analysis is made     

Self-Reported News Attention Does Assess Differential Processing of Media Content: An Experiment on Risk Perceptions Utilizing a Random Sample of U.S. Local Crime and Accident News

Evidence for media effects in survey research often depends upon measures of self-reported attention to various types of media content, under the assumption that such attention measures gauge the extent of cognitive processing of content. However, effects associated with self-reports of attention might often be due to reverse causation (the attitude or knowledge tested as the outcome might in fact give rise to self-reports of greater attention) or third variable effects. To better assess whether self-reported attention to content actually measures differential processing of content, an experiment was conducted in the context of media influences on health and safety risk perceptions. A pool of 120 eligible news stories concerning violent crime, car crashes, and other unintentional injuries was randomly selected from a national random sample of such news coverage. These stories were manipulated to contain or not contain reference to alcohol as a contributing factor in the incident. Consistent with predictions and prior cross-sectional survey results, self-reports of attention and the exposure treatment interacted in estimating concern about alcohol-related risks, with the pattern of results suggesting that between-participant differences in self-reports of attention in fact reflected differences in processing of the message. Methodological advantages of using random samples of messages in experiments for inference are also discussed.     

Surface activation using oxygen and nitrogen radical for Ge-Si Avalanche photodiode integration

In this work, an alternative method for producing the single crystalline Ge-Si Avalanche photodiodes (APD) with low thermal budget was investigated. Structural and electrical investigations show that low temperature Ge to Si wafer bonding can be used to achieve successful APD integration. Based on the surface chemistry of the Ge layer, the buried interfaces were investigated using high resolution transmission electron microscopy as a function of surface activation after low temperature annealing at 200 and 300 °C. The hetero-interface was characterized by measuring forward and reverse currents.