Organic inverter: Theoretical analysis using load matching technique

This paper reports the analysis of key parameters affecting voltage transfer characteristics of pseudo PMOS organic inverters. Pentacene has been used as active material for PMOS Organic Thin Film transistor (OTFT). We have used two different inverter configurations for thorough analysis. Each configuration comprises of an enhancement mode driver (V_Threshold = −9.7 V) and a depletion mode load (V_Threshold = 11.7 V). First configuration has its source and gate terminals shorted. While, second configuration differs with its drain and gate terminals shorted. In order to surmise the theoretical performance of the inverters, we have used load matching technique. After investigating various parameters such as inverting gain, noise margin values (immunity to noise error signals) and threshold voltage value, influencing the voltage inverting efficiency of the two configurations mentioned above, it was found that an inverter with shorted source-gate load configuration is better of the two due to privileges such as saturation mode operation of load, low driver current with early saturation of enhancement mode driver, which facilitates full swing output voltage operation. Second configuration with shorted drain-gate load, lacks saturation mode operation of load and fails to deliver high voltage swing along with acceptable noise margin values and inverting gain.     

An optimal linear and elliptical antenna array design using black widow optimisation for 5G communication

This research illustrates a precise linear and elliptical antenna array design for synthesising the optimal far-field radiation pattern in the fifth-generation (5G) communication spectrum using a meta-heuristic optimisation technique known as black widow optimisation (BWO). 5G communication is an emerging technology with revolutionary changes in the wireless communication system with ultra-high data rate, enhanced capacity, low latency and good quality of service. An accurate antenna array design for an ideal far-field radiation pattern synthesis with a suppressed side lobe level (SLL) value and half power beam width (HPBW) is the most crucial aspect of 5G communications. A suppressed SLL is necessary to reduce interference in the entire side lobe region, whereas a low HPBW is required for long-distance communication. Here, the BWO is employed to find the optimal feeding current to each array element to lower the SLL and the HPBW value. The BWO algorithm sustains impeccable equity between the exploration and exploitation stages to impact different potential regions of the search space and generate new solutions to attain the global optima by evading the trap of local optima. The design examples of the linear antenna array (LAA) and elliptical antenna array (EAA) are illustrated in this article by applying the optimal feeding currents to each array element. Compared to the uniform antenna array and methodologies described in the recently published literature, the results obtained utilising the BWO algorithm for designing the LAAs and EAAs demonstrate a substantial development in the reduction of SLL and HPBW.     

Characteristics of a variable length ring oscillator and its use in PLL based systems

This paper describes the properties of a multiplexer based variable length ring oscillator and the effects of using it as a voltage controlled oscillator (VCO) in a phase locked loop (PLL) based system. The application of the proposed VCO in a PLL used as an FM demodulator or as a frequency synthesizer has been examined and it has been shown that the length control facility of the VCO could be used for improving the performances of those systems. Hardware experimental results confirm the predictions regarding the performance enhancement.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect

In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8 V, digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8 Gb/s data transfer rate over a FR4 PCB trace of length 7.5 in. for a target bit-error rate (BER) of 10⁻¹². The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100 MHz to 20 GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are and 5.34 mV, respectively. The standalone power consumption of the hybrid is 14.64 mW.     

Development of cardiac prescreening device for rural population using ultralow-power embedded system

The invention is inspired by the desire to understand the opportunities and expectations of developing economies in terms of healthcare. The designed system is a point-of-care (POC) device that can deliver heart-care services to the rural population and bridge the rural-urban divide in healthcare delivery. The product design incorporates several innovations including the effective use of adaptive and multiresolution signal-processing techniques for acquisition, denoising, segmentation, and characterization of the heart sounds (HS) and murmurs using an ultralow-power embedded Mixed Signal Processor. The device is able to provide indicative diagnosis of cardiac conditions and classify a subject into either normal, abnormal, ischemic, or valvular abnormalities category. Preliminary results demonstrated by the prototype confirm the applicability of the device as a prescreening tool that can be used by paramedics in rural outreach programs. Feedback from medical professionals also shows that such a device is helpful in early detection of common congenital heart diseases. This letter aims to determine a framework for utilization of automated HS analysis system for community healthcare and healthcare inclusion.     

Tissue-Engineered Vascular Grafts: Emerging Trends and Technologies

Vascular tissue engineering has made prodigious progress in recent years by converging multidisciplinary approaches. Latest technological advancements foster the development of next-generation tissue-engineered vascular grafts (TEVGs) for treating various vasculopathies. While traditional therapeutic methods rely on bypassing the severely damaged vessels with synthetic counterparts with no growth potential, contemporary perspectives focus on biodegradable conduits bestowing an inherent remodeling capability. This review highlights emerging innovative trends and technologies adopted to pragmatically fulfill current scientific needs while improving overall TEVG performance in pre-clinical and clinical settings. A comprehensive overview of various milestones achieved in the past few decades is first summarized, followed by an appraisal of the significant hurdles for clinical translation. The latest techniques to rationally address critical challenges, viz., intimal hyperplasia, thrombosis, constructive graft remodeling, and adequate neo-tissue formation are discussed. Finally, an update on ongoing clinical trials is provided and future perspectives required to persuade TEVGs to become a clinical reality are delineated.     

CL-AGKA: certificateless authenticated group key agreement protocol for mobile networks

Wireless Networks - Wireless group communication has gained much popularity recently due to the increase in portable, lightweight devices. These devices are capable of performing group...     

Simulation, modeling, and crystal growth of Cd0.9Zn0.1Te for nuclear spectrometers

High-quality, large (10 cm long and 2.5 cm diameter), nuclear spectrometer grade Cd_0.9Zn_0.1Te (CZT) single crystals have been grown by a controlled vertical Bridgman technique using in-house zone refined precursor materials (Cd, Zn, and Te). A state-of-the-art computer model, multizone adaptive scheme for transport and phase-change processes (MASTRAP), is used to model heat and mass transfer in the Bridgman growth system and to predict the stress distribution in the as-grown CZT crystal and optimize the thermal profile. The model accounts for heat transfer in the multiphase system, convection in the melt, and interface dynamics. The grown semi-insulating (SI) CZT crystals have demonstrated promising results for high-resolution room-temperature radiation detectors due to their high dark resistivity (ρ≈2.8 × 10¹¹ Θ cm), good charge-transport properties [electron and hole mobility-life-time product, μτ_e≈(2–5)×10⁻³ and μτ_h≈(3–5)×10⁻⁵ respectively, and low cost of production. Spectroscopic ellipsometry and optical transmission measurements were carried out on the grown CZT crystals using two-modulator generalized ellipsometry (2-MGE). The refractive index n and extinction coefficient k were determined by mathematically eliminating the ∼3-nm surface roughness layer. Nuclear detection measurements on the single-element CZT detectors with ²⁴¹Am and ¹³⁷Cs clearly detected 59.6 and 662 keV energies with energy resolution (FWHM) of 2.4 keV (4.0%) and 9.2 keV (1.4%), respectively.     

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18 μm CMOS process to test the topology with a prototype global interconnect having a length of 10 mm. Power consumption of the transceiver for a data rate of 2.5 Gbps data is 2 mW. This gives an energy efficiency of 0.8 pJ/b.