Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

IC—V100电台锁相环频率合成器

本文从频率合成器的结构、功能入手,详细阐述了频率编程的原理及方法。     

Load-capacity interference and the bathtub curve

Load-capacity (stress-strength) interference theory is used to derive a heuristic failure rate for an item subjected to repetitive loading which is Poisson distributed in time. Numerical calculations are performed using Gaussian distributions in load and capacity. Infant mortality, constant failure rate (Poisson failures), and aging are shown to be associated with capacity variability, load variability, and capacity deterioration, respectively. Bathtub-shaped failure rate curves are obtained when all three failure types are present. Changes in load or capacity distribution parameters often strongly affect the quantitative behavior of the failure-rate curves, but they do not affect the qualitative behavior of the bathtub curve. Neither is it likely that the qualitative behavior will be affected by the use of nonGaussian distributions. The numerical results, however, indicate that infant mortality and wear-out failures interact strongly with load variability. Thus bathtub curves arising from this model cannot be represented as simple superpositions of independent contributions from the three failure types. Only if the three failure types arise from independent failure mechanisms or in different components is it legitimate simply to sum the failure rate contributions     

Design considerations for Rowland circle gratings used in photonicintegrated devices for WDM applications

Design issues of photonic integrated devices for WDM applications based on Rowland circle gratings have been studied. Effects of grating period, diffraction order, grating aperture (size), and Rowland circle size on device performance are discussed. The point spread function of a typical Rowland circle grating is evaluated numerically which yields an optical image (spot) size of several microns in diameter. Our study shows that there is a tradeoff between channel dispersion and feedback efficiency in choosing the grating period when a Rowland circle grating is used as the wavelength-selective element for a parallel-waveguide-type wavelength division multiplexing device     

Performance and reliability enhancement for CVD tungsten polycidedCMOS transistors due to fluorine incorporation in the gate oxide

The impacts of CVD tungsten polycide (WSi_x) on MOSFET performance and reliability are studied in this letter. The WSi_x process is shown to enhance the S/D lateral extent for both N- and P-channel devices via C_GD and L_eff measurements, confirming previous suspicion. This enhanced S/D extent is found to be easily modulated by drain-to-gate bias, which is favorable for achieving both higher drive currents and higher S/D punch-through voltages than those of non-WSi_x devices. Both electron and hole mobility for the WSi_x device are also slightly higher and closer to the published data compared to the non-WSi_x case. These effects together yield about >5% improvement for nMOSFET and >10% improvement for pMOSFET in drive current at a given punch-through voltage. The channel hot-electron lifetime for the n-channel WSi_x device is about 10 times higher than that of the non-WSi_x one. These enhancements in both performance and reliability make the WSi_x device very attractive fog VLSI CMOS technologies     

Design of a product quality control system based on the use of data mining techniques

In recent years industries have increasingly used customer relationship labor in management as a tool to improve their position in the marketplace. This research involves using a data warehouse, decision-tree-based data mining, and neural network pattern classification analysis to isolate the causes of non-conformity in IC packaging. The correctness of the classification analysis produced using the two methods is compared. Our objective is to establish an information analysis system, that is able to quickly identify the causes of problems thereby reducing the time taken to solve quality-related problems. It is shown that predictions made about the target group using decision tree analysis are more accurate than those made by neural network classification, indicating that decision tree analysis is an effective means of classification analysis of a company's quality problems.