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991.
992.
993.
SiNx/InP/InGaAs doped channel passivated heterojunction insulated gate field effect transistors (HIGFETs) have been fabricated for the first time using an improved In-S interface control layer (ICL). The insulated gate HIGFETs exhibit very low gate leakage (10 nA@VGS =±5 V) and IDS (sat) of 250 mA/mm. The doped channel improves the DC characteristics and the HIGFETs show transconductance of 140-150 mS/mm (Lg=2 μm), ft of 5-6 GHz (Lg=3 μm), and power gain of 14.2 dB at 3 GHz. The ICL HIGFET technology is promising for high frequency applications 相似文献
994.
K''Andrea C. Bickerstaff Michael J. Schulte Earl E. Swartzlander 《The Journal of VLSI Signal Processing》1995,9(3):181-191
As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products
and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are
then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction
scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction
scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction
of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers.
Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead
for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction
in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8
to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to
33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers. 相似文献
995.
Kizilyalli I.C. Rambaud M.M. Duncan A. Lytle S.A. Thoma M.J. 《Electron Device Letters, IEEE》1995,16(10):457-459
The trade-off between threshold voltage (Vth) and the minimum gate length (Lmin) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale Vth and Lmin for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor Vth for a smaller Lmin results in faster circuits for low supply voltage (3.3 to 1.8 V) n+-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor Vth (absolute value) is approximately 0.85-0.90 V 相似文献
996.
Occlusion of large atrial septal defects with a centering buttoned device: early clinical experience
EB Sideris M Leung JH Yoon CR Chen R Lochan AM Worms C Rey B Meier 《Canadian Metallurgical Quarterly》1996,131(2):356-359
A feasibility clinical study was conducted for the transcatheter occlusion of large ostium secundum atrial septal defects with the centering buttoned device. The centering buttoned device is a modification of the regular buttoned device in which a centering counter-occluder is sutured at the central 40% portion of the occluder. During centering it is stretched, forming a parachute-shaped structure and pulling the occluder over the center of the defect. During buttoning, the counter-occluder forms a double figure eight, opposing the right atrial side of the atrial septum. Occlusion was performed in 12 patients aged 6 to 56 years. All had been rejected for transcatheter occlusion by the regular buttoned device, because of either their defect size or the lack of adequate septal rim. The defect size varied between 23 and 31 mm, and the device size varied between 45 and 60 mm. Nine had immediate effective occlusions of their defects and three residual shunts. One patient with unbuttoning had hemolysis at 2 weeks and underwent surgery. Early results of the transcatheter occlusion of large atrial septal defects are promising, and larger clinical trials are justified. 相似文献
997.
M Schietroma A Risetti F Carlei MV Santirocco F Muzi G Maggi C De Santis CL Recchia D Iannucci R Rampa M Simi 《Canadian Metallurgical Quarterly》1996,48(4):43-46
Adhesions have been suggested as a possible cause of chronic abdominal pain, but the reports of their etiological role conflict. Lysis of adhesions has been proposed as the therapeutic modality of choice, although the reports of success are controversial. The aim our prospective study was to determine whether laparoscopic adhesiolysis ameliorates chronic abdominal pain in patients with abdominal adhesions. Forty-one patients with chronic abdominal pain lasting for more than 6 months, but with no abnormal findings other than adhesions found at laparoscopy, underwent laparoscopic adhesiolysis. 37 patients (90.2%) were available for follow-up after a median time interval of 18 months (range: 12-41 months). Twenty-two patients (59.4%) were free from abdominal pain and 9 (24.3%) patients reported significant amelioration of their pain. Six (16.2%) patients had no amelioration. In conclusion the laparoscopy is an effective tool for the evaluation of patients with chronic abdominal pain, and laparoscopic adhesiolysis cures of ameliorates chronic abdominal pain in more than 80% of patients. 相似文献
998.
999.
The device degradation under ac and dc stress have been discussed and a relationship between the two has been established,. We have shown that the commonly used lifetime criteria of 10% linear current degradation for 10 years for a transistor under dc stress is overly conservative for representing the circuit operating lifetime. Using experimental and simulated data for inverter chains, we proposed that a meaningful equivalent lifetime based on 10% Idl degradation under dc stress is 1 year lifetime (for a 10 year circuit lifetime based on 54b degradation in ring oscillator frequency). We also compared this criteria to actual circuit degradation for microprocessors and a DRAM. For DSP microprocessors with 0.8 μm LDD transistors, the projected lifetime was more than 200 years at 5.5 V, with a corresponding 10% I dr lifetime of 20 years. For 1 Mb DRAMs with 1 pm LDD transistors, the 5% speed degradation lifetime at 5.5 V was more than 100 years, whereas the individual transistors had 10% Idl lifetime of 4 years. These circuit results support the 10% Idl transistor lifetime. We believe these criterion should be very safe and reasonable for digital IC chips currently in the field, as well as those in future design and development 相似文献
1000.
J. C. Sevy 《Calcolo》1993,30(1):41-68
Explicit error estimates are given for the iterated Boolean sum of a sequence of simultaneous approximants; the rate of convergence
is shown to be improved for smooth functions. The general results are applied in the case of the Bernstein, Durrmeyer and
Stancu operators. 相似文献