基于滤纸富集技术的LIBS污水检测

将滤纸作为基底用于LIBS测定水溶液中的金属元素,分析了不同的滤纸浸泡时间对LIBS信号的影响,以及在不同质量浓度的情况下,分析浸泡时间与信号的关系.以实验室配置的不同浓度的偏砷酸钠溶液为研究对象,对浸泡时间为10s和60s的As元素和Na元素做了探测分析并得到了其定标曲线,初步确定了在As元素和Na元素在不同时间下的检测限分别为:As元素0.379g/L(10s)、0.224g/L(60s);Na元素0.021g/L(10s)、0.018g/L(60s).实验所得的结果为探测工业废水中金属元素的含量提供依据.     

Effects of Ni Additions on the Growth of Cu<Subscript>3</Subscript>Sn in High-Lead Solders

In reactions between solders and Cu, additions of minor alloying elements, such as Fe, Co or Ni, to solders often reduce the Cu₃Sn growth rate. Nevertheless, the mechanism for this effect remains unresolved. To provide more experimental observations that are essential for uncovering this mechanism, growth of Cu₃Sn in the reaction between Cu and high-lead solders with or without Ni additions has been studied. The solders used for this study were 10Sn-90Pb and 5Sn-95Pb doped with 0 wt.%, 0.03 wt.%, 0.06 wt.%, 0.1 wt.% or 0.2 wt.% Ni. Reaction conditions included one reflow at 350°C for 2 min and solid-state aging at 160°C for up to 2000 h. The effect of Ni on the growth of Cu₃Sn is discussed in detail based on the experimental results.     

Phase Equilibria in the Sn-Ni-Zn Ternary System: Isothermal Sections at 200°C, 500°C,and 800°C

In the electronic packaging field, the Sn-Zn alloy system has been recommended as a high-temperature Pb-free solder. There is a need for thermodynamic data on the Sn-Ni-Zn ternary system. Such data would serve as a basis for understanding the interfacial reaction between Sn-Zn high-temperature solder and Ni substrates and for thermodynamically evaluating the proper composition level of Ni and Zn in Sn-based solder. This study has investigated the phase equilibria of the Sn-Ni-Zn ternary system at 800°C, 500°C, and 200°C (for Ni composition of less than 60 at.%). Scanning electron microscopy (SEM), x-ray diffraction (XRD), and electron probe microanalysis (EPMA) were used to identify the equilibrium phases. On the basis of the experimental data and thermodynamic parameters, the isothermal sections of the Sn-Ni-Zn ternary system have been described, considering the ternary solubility in the binary phases and newfound ternary phases τ1 (Sn₃Ni₄Zn₃) and τ2 (Sn₄Ni₄Zn₂).     

Electrical characteristics of nMOSFETs fabricated on hybrid orientation substrate with amorphization/templated recrystallization method

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (1 1 0) crystal orientation layer bonded to a bulk (1 0 0) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. However, the material quality of nMOSFETs regions, which has been undergone amorphization/templated recrystallization (ATR) process for transforming the Si surface into (1 0 0) orientation, is still a concern because the ATR-induced defects (i.e., dislocation loops or threads) at the recrystallization layer, could degrade gate oxide integrity. In this paper, we report an investigation of charge pumping and low-frequency (1/f) noise in HOT nMOSFETs. Devices with the increased anneal time brought out a significant reduction in the charge pumping current and 1/f noise, which indicates ATR-induced defects were suppressed and consequently the “low-trap-density” of the Si/SiO₂ interface. Finally, for the first time, the behavior of 1/f noise for HOT nMOSFETs was investigated, and could be described by a unified model, i.e. a combination of carrier-number fluctuations and mobility fluctuations.     

Novel fingerprinting mechanisms for indoor positioning

As wireless communications and microelectronic technology rapidly develop, diverse applications and services based on smart handheld devices have drawn the attention of researchers. The popularity of Indoor Location Based services and applications has also gradually increased. Therefore, how to improve indoor positioning accuracy becomes a very important issue. Although indoor positioning has been performed using various techniques in recent years, the computational complexity of ensuring positioning accuracy and positioning is an unsolved problem. Current indoor positioning systems typically use only the receiver or the transmitter to obtain the reference point data, and only the K‐Nearest Neighbors (KNN) or Trilateration algorithm is used to perform positioning. Therefore, positioning accuracy is limited by the use of reference point data from a single source and by the positioning algorithm used. The Novel Fingerprinting Mechanisms (NFM) indoor positioning system proposed in this study, however, uses both the receiver and transmitter to obtain positioning data and employs six positioning mechanisms to improve the current positioning accuracy. The experimental results show that the average error distance is 1.18 m in the NFM indoor positioning system. That is the system outperforms both KNN and Trilateration systems, which have average error distances of 1.35 m and 2.23 m, respectively. This study proves that the positioning accuracy is actually improved. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of Parasitic Inductance Reduction in GaN Cascode FET for High‐Efficiency Operation

This paper presents a method of parasitic inductance reduction for high‐speed switching and high‐efficiency operation of a cascode structure with a low‐voltage enhancement‐mode silicon (Si) metal–oxide–semiconductor field‐effect transistor (MOSFET) and a high‐voltage depletion‐mode gallium nitride (GaN) field‐effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.     

红外焦平面探测器暗电流计算

红外焦平面探测器的暗电流一般是在零视场(即盲冷屏)条件下进行测试,但这种测试方法必须改变组件结构,只适用于实验室测试.介绍了一种不需要改变组件结构,仅通过基本的性能测试就可以从理论上分析计算得到红外焦平面器件暗电流的方法.对320×256长波探测器组件的试验结果表明,用该方法得到的暗电流结果与用盲冷屏得到的暗电流结果非常接近,可作为红外焦平面探测器暗电流评估的快捷方法.     

移动应用安全防护技术研究

本文首先分析了移动应用的安全现状,提出了移动应用安全评估方法,包括客户端安全评估、服务器安全评估和业务流程安全评估,最后给出了移动应用典型安全漏洞及其检查方法与加固建议,包括敏感数据暴露、鉴权机制缺陷、代码保护不足、公共组件漏洞和应用配置错误。     

Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs

sSi/Si_0.5Ge_0.5/sSOI quantum-well (QW) p-MOSFETs with HfO₂/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si_0.5Ge_0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature.