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221.
A finite element partitioning scheme has been developed to reduce the computational costs of modeling electrically large geometries. In the partitioning scheme, the cylinder is divided into many sections. The finite element method is applied to each section independent of the other sections, and then the solutions in each section are coupled through the use of the tangential field continuity conditions between adjacent sections. Since the coupling matrix is significantly smaller than the original finite element matrix, it is expected that both the CPU time and memory costs can be significantly reduced. The partitioning scheme is coupled to the bymoment method to account for the boundary truncation. Numerical results are presented to demonstrate the efficiency and accuracy of the method 相似文献
222.
Ta-Sung Lee 《Antennas and Propagation, IEEE Transactions on》1994,42(7):928-935
A new simple method is described for synthesizing low-sidelobe sum and difference patterns with partially adaptive weights. By partially adaptive, we mean that only part of the weights are adapted for simultaneous nulling. These adaptive weights are shared by the sum and difference channels, leading to a significant reduction in the number of variable attenuators/phase shifters used, as compared to the fully adaptive implementation. An objective function is derived that yields different configurations of the shared adaptive weights. Numerical examples are presented to ascertain the efficacy of the new method for both point and extended interference 相似文献
223.
Shih-Hsien Lo Chien-Ping Lee 《Electron Devices, IEEE Transactions on》1994,41(9):1504-1512
A two-dimensional transient simulation of the gate lag phenomenon in GaAs MESFET's has been performed. Our results show that the charge exchanges in the population of the surface states at the ungated access region of FET's are responsible for this slow transient phenomenon. The measured “hole-trap-like” DLTS signal is directly related to the re-emission of the holes, trapped during the filling pulse. Higher gate pulse can cause more serious lag phenomenon due to larger modulation of surface charge density. Devices with shorter N+-gate spacing and lower surface state densities are shown to have less gate lag effect 相似文献
224.
Dyadic Green's functions for determining the electric and magnetic fields in a cylindrical waveguide due to a radially directed infinitesimally short electric dipole are derived. The waveguide is shorted at one end and terminated at a perfectly matched load at the other. Both TE and TM modes are considered. Based on these dyadic Green's functions, the input impedance of a coaxial line fed probe in front of the plunger is derived. The formula is expressed in a closed form. Excellent agreement between theoretical results and experimental data for exciting the TE11 mode in the X band for various probe positions is observed 相似文献
225.
Pd-Ge based ohmic contact to n-GaAs with a TiW diffusion barrier was investigated. Electrical analysis as well as Auger electron
spectroscopy and the scanning electron microscopy were used to study the contact after it was subjected to different furnace
and rapid thermal annealing and different aging steps. All analyses show that TiW can act as a good barrier metal for the
Au/Ge/Pd/n-GaAs contact system. A value of 1.45 × 10−6 Ω-cm2 for the specific contact resistance was obtained for the Au/TiW/Ge/Pd/n-GaAs contact after it was rapid thermally annealed
at 425°C for 90 s. It can withstand a thermal aging at 350°C for 40 h with its ρc increasing to 2.94 × 10−6Ω-cm2 and for an aging at 410°C for 40 h with its ρc increasing to 1.38 × 10−5 Ω-cm2. 相似文献
226.
227.
Negative resistance field-effect transistor (NERFET) devices using either strained InGaAs or unstrained GaAs channel layers have been fabricated. The strained InGaAs channel NERFET's show strong negative differential resistance and large drain current peak-to-valley ratio. The peak-to-valley ratio of the InGaAs channel NERFET is more than 3000 at room temperature and larger than one million (106) at 77 K. The peak-to-valley ratio is controllable by adjusting the collector voltage 相似文献
228.
The current-voltage characteristics of the P-N double quantum well resonant interband tunneling (RIT) diodes in InAlAs-InGaAs system have been improved in this letter. The peak-to-valley current ratio (PVCR) is as high as 144 at room temperature. As we know, this is the highest room temperature PVCR ever reported in any tunneling devices. Moreover, the influence of the central barrier thickness varying from 10 Å to 30 Å on the device characteristics is also studied 相似文献
229.
N. Reissis S. Downes M. Kayser D. Lee G. Bentley 《Journal of materials science. Materials in medicine》1994,5(6-7):402-406
The newly developed silver-enhanced colloidal gold staining method was used in a rabbit model to characterize the repair tissue in large articular cartilage defects filled with a heterocyclic methacrylate polymer. By 6 weeks the resurfacing tissue consisted of highly organized hyaline-like articular cartilage, fully integrated with the adjacent normal cartilage. Immuno-histochemistry detected collagen type ll, keratan sulphate, chondroitin 4-sulphate and chondroitin 6-sulphate in the matrix of the neocartilage. The level to which the polymer plug was recessed apeared to be critical to the overall quality of the repair tissue. Optimum results were obtained when the top surface of the biomaterial was at the level of the subchondral bone, below the level of the surrounding articular cartilage. Other technical aspects of implantation, that also affect the repair, are also discussed. 相似文献
230.
Suk Lee Kyung Chang Lee Man Hyung Lee Harashima F. 《Industrial Electronics, IEEE Transactions on》2002,49(3):693-701
This paper focuses on a method to integrate mobile devices such as a mobile robot, automated guided vehicle, and unmanned container transporter to form an automated material handling system. In this paper, the stationary devices are connected via a Profibus network while the mobile devices are communicating via an IEEE 802.11 wireless LAN. In order to integrate these two networks, a protocol converter is developed on a PC platform that runs two interacting processes with shared internal buffers. The protocol converter performs a role of translator between two different protocols by converting the format of a data frame. In addition to this basic conversion function, the protocol converter has a virtual polling algorithm to reduce the uncertainty involved in accessing the wireless network. Finally, the integrated network. of Profibus and IEEE 802.11 is experimentally evaluated for its data latency and throughput, which shows the feasibility of the Profibus-IEEE 802.11 network for industrial applications involving mobile devices 相似文献